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參數資料
| 型號： | AP7168-SPG-13 |
| 廠商： | DIODES INC |
| 元件分類： | 可調正電壓單路輸出LDO穩(wěn)壓器 |
| 英文描述： | 0.8 V-5 V ADJUSTABLE POSITIVE LDO REGULATOR, 0.8 V DROPOUT, PDSO8 |
| 封裝： | GREEN, SOP-8 |
| 文件頁數： | 3/11頁 |
| 文件大?。?/td> | 461K |
| 代理商： | AP7168-SPG-13 |
AP7168
1.2A LOW DROPOUT REGULATOR WITH POK
AP7168
Document number: DS32019 Rev. 2 - 2
3 of 11
September 2010 Diodes Incorporated
N
Electrical Characteristics
(T
A
= 25
o
C, V
IN
Symbol
= V
OUT
+1V, C
IN
= 1
μ
F, C
OUT
Parameter
= 1
μ
F, V
EN
= 2V, unless otherwise stated)
Test Conditions
I
OUT
= 0
V
EN
= 0V, I
OUT
= 0 (Note 3)
V
OUT
≥
1.5V, I
OUT
= 0.5A
V
OUT
≥
1.5V, I
OUT
= 1A
Min
-1
-3
Typ.
125
0.1
230
500
0.8
0.01
Max
180
1
800
1
3
Unit
μA
μA
mV
mV
V
μA
%
I
Q
Input Quiescent Current
Input Shutdown Current
I
SHDN
V
Dropout
Dropout Voltage
V
REF
I
FB
V
OUT
FB reference voltage
FB leakage
Output Voltage Total Accuracy
OUT
IN
OUT
V
Δ
V
Δ
V
OUT
/ V
OUT
Δ
V
/
Line Regulation
V
IN
= V
OUT
+1V to 5.5V,
I
OUT
= 1mA
0.02
%/V
Load Regulation
Start-up Time, from EN high to POK
high
I
OUT
from 1mA to 1A
V
EN
= 0V to 2.0V, I
OUT
= 100mA,
V
IN
= 3.3V
1kHz, V
IN
= 3.3V, V
OUT
= 1.2V,
I
OUT
= 100mA
V
OUT
= 1.8V, R
OUT
= 0.5
Ω
V
IN
= 3.3V, V
OUT
< 0.2V
V
EN
= 0V or 5.5V
Force 2mA
-1.5
1.5
%
t
ST
190
μs
PSRR
Power Supply Rejection Ratio
60
dB
I
LIMIT
I
SHORT
V
IL
V
IH
I
EN
V
OL
Current limit
Short-circuit Current
EN Input Logic Low Voltage
EN Input Logic High Voltage
EN Input leakage
POK output low voltage
Output voltage (rising) POK thresholdrising
1.2
1.4
1.6
750
0.01
100
A
mA
V
V
μA
mV
0.4
1
200
V
POK_TH_UP
V
IN
= 3.3V, V
OUT
= 1.2V
V
POK
= 5.5V
87%
92%
97%
V
ref
V
POK_Hys
POK deglitch
I
POK_LK
T
SHDN
T
HYS
Output voltage POK hysteresis
POK leakage current
Thermal shutdown threshold
Thermal shutdown hysteresis
Thermal Resistance Junction-to-
Ambient
4%
160
0.01
145
25
V
ref
μs
μA
°
C
°
C
1
θ
JA
SOP-8L-EP (Note 4)
27
o
C/W
Notes:
3. POK pin must be disconnected from IN pin.
4
. Test condition for SO-8EP:
Device mounted on 2" x 2" FR-4 substrate PCB, 2oz copper, with minimum recommended pad on top
layer and thermal vias to bottom layer ground plane.
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