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參數(shù)資料
| 型號(hào)： | AP1250CMP |
| 廠商： | ADVANCED POWER ELECTRONICS CORP |
| 元件分類： | 可調(diào)正電壓?jiǎn)温份敵鰳?biāo)準(zhǔn)穩(wěn)壓器 |
| 英文描述： | ADJUSTABLE POSITIVE REGULATOR, PDSO8 |
| 封裝： | ROHS COMPLIANT, ESOP-8 |
| 文件頁(yè)數(shù)： | 3/5頁(yè) |
| 文件大?。?/td> | 421K |
| 代理商： | AP1250CMP |
3
Application Information
Input Capacitor and Layout Consideration
Place the input bypass capacitor as close as
possible to the
AP1250C
MP
. A low ESR capacitor
larger than 470uF is recommended for the input
capacitor. Use short and wide traces to minimize
parasitic resistance and inductance.
Inappropriate layout may result in large parasitic
inductance
and
cause
undesired
oscillation
between
AP1250C
MP
and the preceding power
converter.
Consideration while designs the resistance of
voltage divider
Make sure the sinking current capability of
pull-down NMOS if the lower resistance was
chosen so that the voltage on V
REFEN
is below 0.2V.
In addition, the capacitor and voltage divider form
the lowpass filter. There are two reasons doing this
design; one is for output voltage soft-start while
another is for noise immunity.
Thermal Consideration
AP1250C
MP
regulators have internal thermal limiting
circuitry designed to protect the device during
overload conditions.For continued operation, do not
exceed maximum operation junction temperature
125
℃
. The power dissipation definition in device is:
P
D
= (V
IN
- V
OUT
) x I
OUT
+ V
IN
x I
Q
The maximum power dissipation depends on the
thermal resistance of IC package, PCB layout, the
rate of surroundings airflow and temperature
difference between junction to ambient. The
maximum power dissipation can be calculated by
following formula:
P
D(MAX)
= ( T
J(MAX)
-T
A
) /
Θ
JA
Where T
J(MAX)
is the maximum operation junction
temperature 125
℃
, T
A
is the ambient temperature
and the
Θ
JA
is the junction to ambient thermal
resistance. The junction to ambient thermal
resistance (
Θ
JA
is layout dependent) for
E
SOP-8
package (Exposed Pad) is 75
℃
/W on standard
JEDEC 51-7 (4 layers, 2S2P) thermal test board.
The maximum power dissipation at T
A
= 25
℃
can
be calculated by following formula:
P
D(MAX)
= (125
℃
- 25
℃
) / 75
℃
/W = 1.33W
The thermal resistance
Θ
JA
of
E
SOP-8 (Exposed
Pad) is determined by the package design and the
PCB design. However, the package design has
been decided. If possible, it's useful to increase
thermal performance by the PCB design. The
thermal resistance can be decreased by adding
copper under the expose pad of
E
SOP-8 package.
We have to consider the copper couldn't stretch
infinitely and avoid the tin overflow.
AP1250CMP
Advanced Power
Electronics Corp.
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