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參數(shù)資料
| 型號(hào)： | AP1250CMP |
| 廠商： | ADVANCED POWER ELECTRONICS CORP |
| 元件分類： | 可調(diào)正電壓?jiǎn)温份敵鰳?biāo)準(zhǔn)穩(wěn)壓器 |
| 英文描述： | ADJUSTABLE POSITIVE REGULATOR, PDSO8 |
| 封裝： | ROHS COMPLIANT, ESOP-8 |
| 文件頁(yè)數(shù)： | 1/5頁(yè) |
| 文件大小： | 421K |
| 代理商： | AP1250CMP |
1
Description
The
AP1250C
MP
is a simple, cost-effective and
high-speed linear regulator designed to generate
termination voltage in double data rate (DDR)
memory system to comply with the JEDEC SSTL_2
and SSTL_18 or other specific interfaces such as
HSTL,
SCSI-2
and
SCSI-3
etc.
devices
requirements. The regulator is capable of actively
sinking or sourcing up to 2A while regulating an
output voltage to within 40mV. The output
termination voltage cab be tightly regulated to track
1/2V
DDQ
by two external voltage divider resistors or
the desired output voltage can be pro-grammed by
externally forcing the REFEN pin voltage.
The
AP1250C
MP
also incorporates a high-speed
differential amplifier to provide ultra-fast response in
line/load transient. Other features include extremely
low initial offset voltage, excellent load regulation,
current limiting in bi-directions and on-chip thermal
shut-down protection.
The
AP1250C
MP
are available in the
E
SOP-8
(Exposed Pad) surface mount packages.
Features
Ideal for DDR-I, DDR-II and DDR-III V
TT
Applications
Sink and Source 2A Continuous Current
Integrated Power MOSFETs
Generates Termination Voltage for SSTL_2, SSTL
_18, HSTL, SCSI-2 and SCSI-3 Interfaces.
High Accuracy Output Voltage at Full-Load
Output Adjustment by Two External Resistors
Low External Component Count
Shutdown for Suspend to RAM (STR) Functionality
with High-Impedance Output
Current Limiting Protection
On-Chip Thermal Protection
Available in
E
SOP-8 (Exposed Pad) Packages
V
IN
and V
CNTL
No Power Sequence Issue
RoHS Compliant and 100% Lead (Pb)-Free
Pin Configuration
Application
Desktop PCs, Notebooks, and Workstations
Graphics Card Memory Termination
Set Top Boxes, Digital TVs, Printers
Embedded Systems
Active Termination Buses
DDR-I, DDR-II and DDR-III Memory Systems
Block Diagram
Pin Description
Pin Name
Pin function
V
IN
Power Input
GND
Ground
V
CNTL
Gate Drive Voltage
REFEN
Reference Voltage input and Chip Enable
V
OUT
Output Voltage
Advanced Power
Electronics Corp.
2A Sink/Source Bus Termination Regulator
AP1250CMP
200901074
GND
REFEN
VOUT
VIN
NC
VCNTL
NC
NC
1
2
3
4
8
7
6
5
ESOP-8 (MP)
(Top View)
GND
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| AP1250GH | 制造商:A-POWER 制造商全稱:Advanced Power Electronics Corp. 功能描述:1.5A / 3A Bus Termination Regulator |
| AP1250GM | 制造商:A-POWER 制造商全稱:Advanced Power Electronics Corp. 功能描述:1.5A / 3A Bus Termination Regulator |
| AP1-251-17 | 制造商:Sensata Technologies 功能描述:AP1-251-17 /Pole # 1 /Prod Family: 0202 |
| AP1-25-17 | 制造商:Sensata Technologies 功能描述:AP1-25-17 /Pole # 1 /Prod Family: 0202 |
| AP1-25-20 | 制造商:Sensata Technologies 功能描述:AP1-25-20 /Pole # 1 /Prod Family: 0202 |
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