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參數(shù)資料
| 型號(hào)： | AN5367FB |
| 廠商： | PANASONIC CORP |
| 元件分類： | 消費(fèi)家電 |
| 英文描述： | NTSC video, chroma, and deflection signal processing circuit |
| 中文描述： | SPECIALTY CONSUMER CIRCUIT, PQFP48 |
| 封裝： | 12 X 12 MM, PLASTIC, QFP-48 |
| 文件頁數(shù)： | 7/22頁 |
| 文件大?。?/td> | 249K |
| 代理商： | AN5367FB |
7
ICs for TV
AN5367FB
I
Electrical Characteristics at T
a
=
25
°
C (continued)
Parameter
Symbol
Conditions
Min
Typ
Max
Unit
Horizontal signal processing
Horizontal stabilized power supply
voltage
V
14
Pin voltage, when power supply pin
input current I
14
=
8 mA
5.7
6.1
6.8
V
Horizontal stabilized power supply
maximum current
I
14
Maximum input current for which power
supply is stabilized
13
mA
Horizontal stabilized power supply
on-state resistance
R
14
On-state resistance, when input current
I
14
=
6 mA to 13 mA
0
14
30
Horizontal output start voltage
V
FHS
Horizontal stabilized power supply
voltage, when horizontal output pulse
becomes 1 V[p-p] or more. Do not
apply other power supply voltage.
4.5
5.2
V
Horizontal output pulse duty
τ
HO
Horizontal output pulse high level duty 46.9
50.0
53.1
%
High-level horizontal output
V
19H
Horizontal output pulse high level
4.0
4.3
4.6
V
Low-level horizontal output
V
19L
f
HO
Horizontal output pulse low level
0.2
0.5
V
Horizontal output free-running
frequency
Horizontal output frequency, when there
is no horizontal sync. separation input
15.45 15.73 16.05
kHz
Hor. pull-in range
f
HP
Frequency at which horizontal sync.
separation input frequency pulls in.
Sync. signal 0.57 V[p-p].
±
500
±
600
Hz
Screen position fluctuation 1
H
POS1
Phase change of horizontal sync. signal
and FBP, H-center (0A): 67
→
60
1.70
2.12
2.55
μ
s
Screen position fluctuation 2
H
POS2
Phase change of horizontal sync. signal
and FBP, H-center (0A): 67
→
6F
1.97
2.46
3.14
μ
s
Hold Down operation level
V
HD
Voltage at which X-ray input pin voltage
holds down. Hold down pin reference
voltage: 6.2 V
5.9
6.2
6.5
V
High-level lock det. output
LD
H
At horizontal AFC unlocked,
RL
=
56 k
4.5
V
Low-level lock det. output
LD
L
At horizontal AFC locked,
RL
=
56 k
0.7
V
BLK-in input threshold voltage
BLK
ST
Pin 18 threshold voltage (BLK is applied
to RGB output stage only)
1.7
2.2
2.7
V
Vertical signal processing
Ver. out pulse width
τ
VO
Pulse width at horizontally/vertically
synchronized state
610
640
670
μ
s
High-level ver. out 1
V
10H1
Vertical output pulse high level
pin 10: open
4.0
4.3
4.6
V
High-level ver. out 2
V
10H2
Vertical output pulse high level
pin 10:
0.2 mA
3.75
4.10
4.60
V
High-level ver. out 3
V
10H3
Vertical output pulse high level
pin 10:
0.5 mA
3.3
3.9
4.6
V
Note) Unless otherwise specified, refer to "
Typical conditions for testing" for the conditions of I
2
C bus and each pin.
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