
On-Chip Routines Source Code
On-Chip FLASH Programming Routines, Rev. 4
Freescale Semiconductor
29
;* 23 bus cycles after this routine is called in the user software.
;* However, the COP timeout might still occur under the following
;* conditions:
;* 1) COP is not serviced within a proper period in user software
;* 2) COP set for short timeout and Read data is sent through PTA0
;* STACK FRAME:
;* SP+1 [G] SADDR(hi) temp storage
;* SP+2 [F] SADDR(lo) temp storage
;* SP+3 SP+1 [E] ByteCount - decrements to zero
;* SP+4 SP+2 [D] # of bad bytes - 0 on return means all were good
;* SP+5 SP+3 [C] Checksum - sum of all data values read
;* SP+6 SP+4 [B] Offset pointer into DATA array in RAM
;* SP+7 SP+5 [A] Verify/Read flag - 1=verify/0=read
;* | | |
;* | | +--reference label in square brackets
;* | +---SP offset when SADDR not on stack
;* +---------SP offset when SADDR on stack for temp storage
;*********************************************************************
RDVRRNG: psha ;verify(1)/Read(0) flag to Stack [A]
clra
psha ;offset pointer into DATA array in
; RAM [B] (initially 0)
; increments from $00 to ByteCount
psha ;initial Checksum to Stack [C]
;calculate total # of bytes
txa ;SADDR(lo) -> A
sub LADDR+1 ;SADDR(lo) - LADDR(lo) -> A
nega ;LADDR(lo) - SADDR(lo) -> A
inca ;change to 1-oriented vs 0-oriented
psha ;# of bytes to Stack [D] (# of bad)
; decrements to zero if all good
psha ;ByteCount to Stack [E]
; counter - decrements to zero
ReadData:
sta COPCTL ;service COP
lda ,x ;data from a FLASH location @ 0,X
tst 5,sp ;check Read/Verify flag [A]
beq Serial ;0 - send data through PTA0
;1 - verify against DATA in RAM
pshx ;push SADDR(lo) to Stack [F]
pshh ;push SADDR(hi) to Stack [G]
ldx 6,sp ;DATA array Pointer(lo) -> X
clrh ;H:X = 0:Pointer(lo)
cmp DATA,x ;compare FLASH data with DATA array
bne NoDataMatch ;if not equal, skip decrement of [D]
dec 4,sp ;data matched so decrement # of bad
NoDataMatch: sta DATA,x ;replace DATA array value with
; value read from FLASH
pulh ;restore SADDR(hi) pointer from [G]
pulx ;now H:X = SADDR, A is FLASH data
bra Checksum ;skip serial send if in Verify mode
Serial: jsr PutByte ;read mode so send data to host
Checksum: add 3,sp ;FLASH data + checksum [C] -> A
sta 3,sp ;update checksum [C] on stack
inc 4,sp ;update offset into DATA array [B]