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參數(shù)資料
| 型號(hào)： | AN231E04 |
| 廠商： | Electronic Theatre Controls, Inc. |
| 英文描述： | Dynamically Reconfigurable dpASP |
| 中文描述： | 動(dòng)態(tài)可重構(gòu)dpASP |
| 文件頁數(shù)： | 8/24頁 |
| 文件大?。?/td> | 445K |
| 代理商： | AN231E04 |
AN231E04 Datasheet – Dynamically Reconfigurable dpASP
DS231000-U001d
- 8 -
1.4
Digital I/O Characteristics, continued (VDD = 3.3v +/-10%, -40 to 85 deg.C unless commented)
1.4.7
MEMCLK/DOUT2 (CMOS Output)
The primary function of this pin is as MEMCLK (Memory Clock), this signal is used as a clock output in circuit designs which
require configuration from an SPI PROM (or SPI EEPROM), please refer to the AN231E04 User Guide for details.
If the MEMCLK signal pin is not required (e.g. a circuit configured from a microcontroller) then via dpASP configuration this pin
can be used as a digital output.
The MEMCLK signal is only active when the dpASP MODE (pin35) is high (tied to VDD).
DOUT2 function cannot be used if dpASP MODE (pin35) is high (tied to VDD).
Parameter
Symbol
Min
Typ
Max
Unit
Comment
Load 10pF//50Kohm to VSS.
This Pin MEMCLK is unused in
this MODE=VSS, there is an
internal weak pull down resistor
Load 100pF//5Kohm to VSS
Output Voltage Low, (MODE
pin 35 = VSS, DOUT2
inactive)
Vol
VSS
-
VSS
mV
Output Voltage Low, (MODE
pin 35 = VSS, DOUT2 active)
Output Voltage Low, (MODE
pin 35 = VDD)
Vol
VSS
-
VSS
mV
Vol
VSS
-
VSS
mV
Load 100pF//5Kohm to VSS
Output Voltage High
Voh
3.28
-
VDD
V
Load 100pF//5Kohm to VSS,
VDD = 3.3V.
Maximum load 100 pF // 5 Kohm
Maximum load 100 pF // 5 Kohm
Pin shorted to VDD.
Th This Pin MEMCLK is unused
when MODE=VSS and DOUT2 is
inactive. Thus No active drive.
Pin shorted to VSS.
This Pin MEMCLK is unused
when MODE=VSS and DOUT2 is
inactive. Thus No active drive.
Pin shorted to VDD.
Current should be limited
externally so that it does not
exceed 3mA
Pin shorted to VSS.
Current should be limited
externally so that it does not
exceed 3mA
Skew at DOUT2 (pin 42) relative to
external signal clock applied to
input pin ACLK (pin 34).
Note; This is only valid when
DOUT2 is selected to output the
CAM clockA, and CAM clockA is
derived from ACLK divided by1.
This is the delay of the comparator
CAM output transition relative to
the exported comparator clock
clock appears on the output pin.
Note, The comparator is clocked
with a user programmable CAM
clock derived from a division of
ACLK
This is the delay of the signal at
the dpASP pin 42, (DOUT2)
relative to the actual internal
transfer event.
This is the delay of the signal at the
dpASP pin 42, (DOUT2) relative to
the actual internal event.
Max. Capacitive Load
Min. Resistive Load
Cmax
Rmin
-
5
-
-
100
-
pF
Kohm
Current Sink, (MODE pin 35 =
VSS & DOUT2 inactive)
Isnk
0.01
0.03
0.05
mA
Current Source, (MODE pin
35 = VSS & DOUT2 inactive)
Isrc
-
-
+/-1
uA
Current Sink,
(MODE pin 35 = VDD
or DOUT2 active)
Isnk
60
100
135
mA
Current Source,
(MODE pin 35 = VDD
or DOUT2 active)
Isrc
50
80
110
mA
Clock skew
(DOUT2 connected to
“clocka”)
CLK
SKEW
-
8.0
-
ns
Comparator skew
(DOUT2 connected to
“comparitor”)
COMP
SKEW
-
25.0
-
ns
RAM transfer delay
(DOUT2 connected to “RAM
transfer Pulse”)
RAM
DELAY
-
20.0
-
ns
Auto-null/Osc start delay
(DOUT2 connected to “Auto-
null/Osc start done” signal)
2
2
see application note AN231002 “Auto-nulling within the AN231E04”
DONE
DELAY
-
40
-
ms
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