參數(shù)資料
型號(hào)： XRT75R12IB
廠商： EXAR CORP
元件分類： 數(shù)字傳輸電路
英文描述： TWELVE CHANNEL E3/DS3/STS-1 LINE INTERFACE UNIT WITH JITTER ATTENUATOR
中文描述： DATACOM, PCM TRANSCEIVER, PBGA420
封裝： 35 X 35 MM, TBGA-420
文件頁(yè)數(shù)： 50/89頁(yè)
文件大?。?/td> 457K
代理商： XRT75R12IB
XRT75R12
REV. P1.0.2
PRELIMINARY
TWELVE CHANNEL E3/DS3/STS-1 LINE INTERFACE UNIT WITH JITTER ATTENUATOR
47
7.2
Whether the LIU is configured for Asynchronous or Synchronous mode, the following descriptions apply. The
synchronous mode requires an input clock (PCLK) to be used as the microprocessor timing reference. Read
and Write operations are described below.
Read Cycle (For Pmode = "0" or "1")
Whenever the local μP wishes to read the contents of a register, it should do the following.
1.
Place the address of the target register on the address bus input pins Addr[7:0].
2.
While the μP is placing this address value on the address bus, the address decoding circuitry should
assert the CS pin of the LIU, by toggling it "Low". This action enables communication between the μP and
the LIU microprocessor interface block.
3.
Next, the μP should indicate that this current bus cycle is a Read operation by toggling the RD input pin
"Low". This action enables the bi-directional data bus output drivers of the LIU.
4.
After the μP toggles the Read signal "Low", the LIU will toggle the RDY output pin "Low". The LIU does this
to inform the μP that the data is available to be read by the μP, and that it is ready for the next command.
5.
After the μP detects the RDY signal and has read the data, it can terminate the Read Cycle by toggling the
RD input pin "High".
6.
The CS input pin must be pulled "High" before a new command can be issued.
Write Cycle (For Pmode = "0" or "1")
Whenever a local μP wishes to write a byte or word of data into a register within the LIU, it should do the follow-
ing.
1.
Place the address of the target register on the address bus input pins Addr[7:0].
2.
While the μP is placing this address value on the address bus, the address decoding circuitry should
assert the CS pin of the LIU, by toggling it "Low". This action enables communication between the μP and
the LIU microprocessor interface block.
3.
The μP should then place the byte or word that it intends to write into the target register, on the bi-direc-
tional data bus D[7:0].
4.
Next, the μP should indicate that this current bus cycle is a Write operation by toggling the
WR
input pin
"Low". This action enables the bi-directional data bus input drivers of the LIU.
5.
After the μP toggles the Write signal "Low", the LIU will toggle the RDY output pin "Low". The LIU does this
to inform the μP that the data has been written into the internal register location, and that it is ready for the
next command.
6.
The CS input pin must be pulled "High" before a new command can be issued.
A
SYNCHRONOUS
AND
S
YNCHRONOUS
D
ESCRIPTION
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