參數(shù)資料
型號: AM79Q021
廠商: Electronic Theatre Controls, Inc.
英文描述: Quad Subscriber Line Audio-Processing Circuit (QSLAC) Devices
中文描述: 四用戶線路音頻處理電路(QSLAC)設備
文件頁數(shù): 12/68頁
文件大?。?/td> 1361K
代理商: AM79Q021
12
Am79Q02/021/031 Data Sheet
ELECTRICAL CHARACTERISTICS
Typical values are for T
A
= 25
°
C and nominal supply voltages. Minimum and maximum values are over the
temperature and supply voltage ranges shown in Operating Ranges.
Notes:
1. The CD1, CD2, C3
C5 outputs are resistive for less than a 0.8 V drop. Total current must not exceed absolute maximum ratings.
2. When the digitizer saturates, a resistor of 50 k
±20 k
is connected either to DGND or to VCCD
(1 diode drop) as
appropriate to discharge the coupling capacitor.
3. When the QSLAC device is in the Inactive state, the analog output will present either a VREF DC output level through a 15 k
resistor (V
MODE
= 0) or a high impedance (V
MODE
= 1).
4. If there is an external DC path from VOUT to VIN with a gain of G
DC
and the AISN has a gain of h
AISN
, then the output offset
will be multiplied by 1/[1
(h
AISN
G
DC
)].
5. Power dissipation in the Inactive state is measured with all digital inputs at V
IH
= V
CC
and V
IL
= DGND and with no load
connected to VOUT
1
, VOUT
2
, VOUT
3
, or VOUT
4
.
Symbol
V
IL
V
IH
I
IL
Parameter Descriptions
Min
Typ
Max
0.8
Unit
Note
Input Low voltage
Input High voltage
Input leakage current
Output Low voltage
CD1
C5 (I
OL
= 4 mA)
CD1
C5 (I
OL
= 8 mA)
TSCA, TSCB (I
OL
=14 mA)
Other digital outputs (I
OL
= 2 mA)
Output High voltage
CD1
C5 (I
OH
= 4 mA)
CD1
C5 (I
OH
= 8 mA)
Other digital outputs (I
OH
= 400
μ
A)
Output leakage current (H
I
= Z state)
Analog input voltage range(AX = 0 dB)
(Relative to VREF)(AX = 6.02 dB)
Offset voltage allowed on VIN
Analog input impedance to VREF300 to 3400 Hz
Current into analog input for input voltages between
3.8 V and 5.0 V
Current out of analog input for input voltages between
0 V and 0.5 V
VOUT output impedance
VOUT
output current (F< 3400 Hz)
VREF output impedance (F < 3400 Hz)
VOUT voltage range(AR = 0 dB)
(Relative to VREF)(AR = 6.02 dB)
VOUT offset voltage (AISN off)
VOUT offset voltage (AISN on)
Linearity of AISN circuitry (input = 0 dBm0)
Power dissipation
All channels active
1 channel active
All channels inactive, (in normal state)
All channels inactive (in low power state)
Input capacitance (Digital)
Output capacitance (Digital)
Power supply rejection ratio (1.02 kHz, 100 mV
RMS
, ei-
ther path, GX = GR = 0 dB)
V
2.0
10
+10
μ
A
V
OL
0.4
0.8
0.4
0.4
V
1
V
OH
V
CCD
0.4 V
V
CCD
0.8 V
2.4
10
1
I
OL
10
μ
A
V
IR
±1.584
±0.792
Vpk
V
IOS
Z
IN
50
0.43
50
3.4
mV
M
I
IP
54
170
μA
2
I
IN
50
170
2
Z
OUT
I
OUT
Z
REF
1
10
4
130
3
4
70
mApk
k
V
OR
±1.584
±0.792
Vpk
V
OOS
V
OOSA
LIN
AISN
40
80
0.25
40
80
0.25
mV
4
LSB
PD
200
70
18
6
260
130
25
12
mW
5
C
I
C
O
15
15
pF
PSRR
40
dB
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