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參數(shù)資料
| 型號： | AM79C982 |
| 廠商： | Advanced Micro Devices, Inc. |
| 英文描述： | basic Integrated Multiport Repeater (bIMR) |
| 中文描述： | 基本綜合多端中繼器（bIMR） |
| 文件頁數(shù)： | 21/26頁 |
| 文件大?。?/td> | 254K |
| 代理商： | AM79C982 |
AMD
PRELIMINARY
1–23
Am79C982
Minimum Mode
The Minimum Mode reconfigures the bIMR device Man-
agement Port and is intended to provide support for the
low end, non-managed repeaters, requiring minimal ex-
ternal logic to provide LED indication of:
I
Twisted Pair Ports Link Status indication and AUI
Loopback Status
I
Port Partitioning Status
I
Twisted Pair Ports Receiver Polarity Status and
AUI SQE Test Error Status
I
Port Bit Rate Error Status
The Minimum Mode is selected by controlling the state
of the TEST pin while
RST
is asserted. If TEST is High
(asserted), while reset is active (
RST
LOW), then Mini-
mum Mode is selected. The state of SI pin, at the de-
assertion of the
RST
signal, determines whether the
bIMR chip is to be programmed for Automatic Polarity
Detection/Correction.
When entering the Minimum Mode, the TEST input has
to be deasserted on the rising edge of reset. A maximum
delay of 100 ns is allowed to account for slow devices.
The following table summarizes the different modes
available.
Test
SI
Functions
0
0
Normal Management Mode
0
1
Normal Management Mode
1
0
Minimum Mode, Receive
Polarity Correction disabled
1
1
Minimum Mode, Receive
Polarity Correction enabled
In Minimum Mode, the SO pin is used to serially output
the various status information based on the state of the
SI and SCLK pins. A summary of the status information
is provided in the following table.
SCLK
SI
SO Output
0
0
TP Ports Receive Polarity Status +
AUI SQE Test Error Status.
0
1
Bit Rate Error (all ports).
1
0
TP Ports Link Status + AUI
LoopBack Status
1
1
Port Partitioning Status (all ports)
When SI = 0 then SO will output the related AUI status
bits (LoopBack or SQE), followed by the 8 (4) TP status
bits (Link or Polarity), starting with the TP port 0.
When SI = 1, the Port Partitioning Status or Port Bit Rate
Error Status are scanned out with the AUI first and TP
ports following. TP Port 0 is scanned out first.
Note that the Bit Rate Error, AUI Loopback, and AUI
SQE Test Error status bits stay set until they are
scanned out.
The state of SI and SCLK inputs is checked at the end of
every STR cycle. The rising edge of the X1 clock, occur-
ring before falling edge of STR, is used to strobe in the
state of the SI and SCLK pins.
In this Minimum Mode, the Management Port mode is
not active. To exit the Minimum mode, the bIMR device
must reset into the normal Management Port mode.
Am79C982
bIMR8 Chip
XTAL
OSC
CK
D
Q
ASYNC
RESET
X1
X2
RST
STR
SO
CLR
CK
Q
Q
D
1/2 ’74
TCK
CK
SI
SIPO
CK
T
P
7
T
P
6
T
P
5
T
P
0
A
U
I
1/2 ’74
TCK
SCLK
SI
19406B-10
Register
TEST
Figure 3. bIMR8 LED Display Design using Minimum Mode
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