參數(shù)資料
型號(hào)： AM79C982
廠商： Advanced Micro Devices, Inc.
英文描述： basic Integrated Multiport Repeater (bIMR)
中文描述： 基本綜合多端中繼器（bIMR）
文件頁(yè)數(shù)： 20/26頁(yè)
文件大?。?/td> 254K
代理商： AM79C982
AMD
PRELIMINARY
1–22
Am79C982
B Bit Rate Error. This bit is set to 1 if there has been an
instance of FIFO Overflow or Underflow, caused by
data received at the AUI port. This bit is cleared when
the status is read.
S SQE Test Status. This bit is set to 1 if SQE Test is
detected by the bIMR chip. This bit is cleared when
the status is read. A MAU attached to a repeater
must have SQE Test disabled. This bit is set even if
the AUI port is disabled or partitioned.
L Loop Back Error. The MAU attached to the AUI is
required to loopback data transmitted to DO onto the
DI circuit. If loopback carrier is not detected by the
bIMR device, then this bit is set to 1 to report this
condition. This bit is cleared when the status is read.
For a repeater this is the only indication of a broken
or missing MAU.
TP Port Partitioning Status
SI data:
SO data:
SO data:
10000000
P
7
....................P
0
(bIMR8)
P
3
X P
2
X P
1
X P
0
(bIMR4)
X = don’t care
Pn = 0
TP port n partitioned
Pn = 1
TP port n connected
The partitioning Status of all four or eight TP ports are
accessed by this command. If a port is disabled, reading
it partitioning status will indicate that it is connected.
Bit Rate Error Status of TP Ports
SI data:
SO data:
SO data:
10100000
E
7
....................E
0
(bIMR8)
E
3
X E
2
X E
1
X E
0
(bIMR4)
X = don’t care
This allows a single command to be used to report Bit
Rate Error condition (FIFO Overflow or Underflow) of all
Twisted Pair ports. The 8 bits (4 bits) of the output pat-
tern correspond to each of the 8 TP (4 TP) ports, with
least significant bit corresponding to port 0.
The status bit for a port is set to 1 if there has been an
instance when data received from that port has caused
a FIFO error.
All status bits stay set until the status is read.
Link Test Status of TP Ports
SI data:
SO data:
SO data:
11010000
L
7
....................L
0
(bIMR8)
L
3
X L
2
X L
1
X L
0
(bIMR4)
X = don’t care
Ln = 0
Ln = 1
TP Port n in Link Test Fail
TP Port n in Link Test Pass
The Link Test Status of all eight (four) TP ports are ac-
cessed by this command. A disabled port continues to
report correct Link Test Status. Re-enabling a disabled
port causes the port to be placed into Link Test Fail
state. This ensures that packet fragments received on
the port are not repeated to the rest of the network.
Receive Polarity Status of TP Ports
SI data:
SO data:
SO data:
11100000
P
7
....................P
0
(bIMR8)
P
3
X P
2
X P
1
X P
0
(bIMR4)
X = don’t care
Pn = 0
Pn = 1
TP Port n Polarity Correct
TP Port n Polarity Reversed
The statuses of all eight (four) TP port polarities are ac-
cessed with this command. The bIMR chip has the abil-
ity to detect and correct reversed polarity on the TP
ports’ RXD+/– pins. If the polarity is detected as re-
versed for a TP port, then the bIMR chip will set the ap-
propriate bit in this command’s result byte only if the
Polarity Reversal Function is enabled for that port.
MJLP Status
SI data:
SO data:
11110000
M00000000
Each bIMR chip contains an independent MAU Jabber
Lock Up Protection Timer. The timer is designed to in-
hibit the bIMR device transmit function, if it has been
transmitting continuously for more than 65536 Bit
Times. The MJLP Status bit (M) is set to 1 if this hap-
pens. This bit remains set and is only cleared when the
MJLP status is read by using this command.
Version
SI data:
SO data:
11111111
XXXX0001
This command (1111 1111) can be used to determine
the device version.
The bIMR chip responds by the bit pattern: XXXX 0101
相關(guān)PDF資料
PDF描述
AM79C982-4JC basic Integrated Multiport Repeater (bIMR)
AM79C982-8JC basic Integrated Multiport Repeater (bIMR)
AM79C983AKC Integrated Multiport Repeater 2 (IMR2⑩)
AM79C984 enhanced Integrated Multiport Repeater (eIMR⑩)
AM79C984A enhanced Integrated Multiport Repeater (eIMR⑩)
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