參數(shù)資料
型號(hào): AM79C981
廠商: Advanced Micro Devices, Inc.
英文描述: Integrated Multiport Repeater Plus⑩ (IMR+⑩)
中文描述: 綜合多端中繼器加⑩(死亡率⑩)
文件頁(yè)數(shù): 27/40頁(yè)
文件大?。?/td> 347K
代理商: AM79C981
AMD
PRELIMINARY
1–97
Am79C981
SWITCHING CHARACTERISTICS over operating ranges unless otherwise specified
Parameter
Symbol
Parameter Description
Test Conditions
Min
Max
Unit
Clock and Reset
t
X1
X1 Clock Period
49.995
50.005
ns
t
X1H
X1 Clock HIGH
20
30
ns
t
X1L
X1 Clock LOW
20
30
ns
t
X1R
X1 Clock Rise Time
10
ns
t
X1F
X1 Clock Fall Time
10
ns
t
PRST
Reset pulse width after power on
(
RST
pin LOW)
150
μ
s
t
RST
Reset pulse width
(
RST
pin LOW)
4
μ
s
t
RSTSET
RST
HIGH setup time with
respect to X1 Clock
20
ns
t
RSTHLD
RST
LOW hold time with
respect to X1 Clock
0
ns
Management Port
t
SCLK
SCLK Clock Period
100
ns
t
SCLKH
SCLK Clock HIGH
30
ns
t
SCLKL
SCLK Clock LOW
30
ns
t
SCLKR
SCLK Clock Rise Time
10
ns
t
SCLKF
SCLK Clock Fall Time
10
ns
t
SISET
SI input setup time with respect to SCLK
rising edge
10
ns
t
SIHLD
SI input hold time with
respect to SCLK rising edge
10
ns
t
SODLY
SO output delay with
respect to SCLK rising edge
C
L
= 100 pF
40
ns
t
X1HCRS
X1 rising edge to CRS valid
C
L
= 100 pF
5
40
ns
t
X1HSTH
X1 rising edge to STR HIGH
C
L
= 100 pF
40
ns
t
X1HSTL
X1 rising edge to STR LOW
C
L
= 100 pF
40
ns
t
TESTSET
TEST input setup time with respect to
SCLK rising edge
10
ns
t
TESTHLD
TEST input hold time with respect to
SCLK rising edge
10
ns
t
STRSET
STR setup time
5
ns
t
STRHLD
STR hold time
12
ns
Expansion Port
t
X1HRL
X1 rising edge to
REQ
driven LOW
C
L
= 100 pF
14
40
ns
t
X1HRH
X1 rising edge to
REQ
driven HIGH
C
L
= 100 pF
14
40
ns
t
X1HDR
X1 rising edge to DAT/JAM driven
C
L
= 100 pF
14
40
ns
t
X1HDZ
X1 rising edge to DAT/JAM not driven
C
L
= 100 pF
14
40
ns
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