參數(shù)資料
型號(hào)： AM79C972BVIW
廠商： ADVANCED MICRO DEVICES INC
元件分類： 微控制器/微處理器
英文描述： PCnet⑩-FAST+ Enhanced 10/100 Mbps PCI Ethernet Controller with OnNow Support
中文描述： 5 CHANNEL(S), 100M bps, LOCAL AREA NETWORK CONTROLLER, PQFP176
封裝： TQFP-176
文件頁(yè)數(shù)： 122/130頁(yè)
文件大?。?/td> 1580K
代理商： AM79C972BVIW
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122
Am79C972
This bit was called DTCR in the
LANCE (Am7990) device.
Read/Write accessible only when
either the STOP or the SPND bit
is set.
2
LOOP
Loopback Enable allows the
Am79C972 controller to operate
in full-duplex mode for test pur-
poses. The setting of the full-
duplex control bits in BCR9 have
no effect when the device oper-
ates in loopback mode. When
LOOP = 1, loopback is enabled.
In combination with INTL and
MIIILP, various loopback modes
are defined as follows in Table
21.
Refer to
Loop Back Operation
section for more details.
Read/Write accessible only
when either the STOP or the
SPND bit is set. LOOP is cleared
by H_RESET or S_RESET and
is unaffected by STOP.
1
DTX
Disable
Am79C972 controller not access-
ing the Transmit Descriptor Ring
and, therefore, no transmissions
are attempted. DTX = 0, will set
TXON bit (CSR0 bit 4) if STRT
(CSR0 bit 1) is asserted.
Transmit
results
in
Read/Write accessible only when
either the STOP or the SPND bit
is set.
0
DRX
Disable Receiver results in the
Am79C972 controller not access-
ing the Receive Descriptor Ring
and, therefore, all receive frame
data are ignored. DRX = 0, will
set RXON bit (CSR0 bit 5) if
STRT (CSR0 bit 1) is asserted.
Read/Write accessible only when
either the STOP or the SPND bit
is set.
CSR16: Initialization Block Address Lower
Bit
Name
Description
31-16
RES
Reserved locations. Written as
zeros and read as undefined.
15-0
IADRL
This register is an alias of CSR1.
Read/Write accessible only when
either the STOP or the SPND bit
is set.
CSR17: Initialization Block Address Upper
Bit
Name
Description
31-16
RES
Reserved locations. Written as
zeros and read as undefined.
15-0
IADRH
This register is an alias of CSR2.
Read/Write accessible only when
either the STOP or the SPND bit
is set.
CSR18: Current Receive Buffer Address Lower
Bit
Name
Description
31-16
RES
Reserved locations. Written as
zeros and read as undefined.
15-0
CRBAL
Contains the lower 16 bits of the
current receive buffer address at
which the Am79C972 controller
will store incoming frame data.
Read/Write accessible only when
either the STOP or the SPND bit
is set. These bits are unaffected
by H_RESET, S_RESET, or
STOP.
CSR19: Current Receive Buffer Address Upper
Bit
Name
Description
31-16
RES
Reserved locations. Written as
zeros and read as undefined.
15-0
CRBAU
Contains the upper 16 bits of the
current receive buffer address at
which the Am79C972 controller
will store incoming frame data.
Table 21.
Loopback Configuration
LOOP
0
1
1
0
0
1
INTL
0
1
0
0
0
0
MIIILP
0
0
0
0
1
0
Function
GPSI
Normal Operation
Internal Loop
External Loop
Normal Operation
Internal Loop
External Loop
MII
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