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參數(shù)資料
| 型號(hào)： | AM79C972 |
| 廠商： | Advanced Micro Devices, Inc. |
| 英文描述： | PCnet⑩-FAST+ Enhanced 10/100 Mbps PCI Ethernet Controller with OnNow Support |
| 中文描述： | PCnet⑩與OnNow增強(qiáng)10/100 Mbps的快速以太網(wǎng)控制器支持的PCI |
| 文件頁(yè)數(shù)： | 62/130頁(yè) |
| 文件大?。?/td> | 1580K |
| 代理商： | AM79C972 |
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62
Am79C972
frame data in the FIFO can be overwritten as soon as it
is transmitted.
If 16 total attempts (initial attempt plus 15 retries) fail,
the Am79C972 controller sets the RTRY bit in the cur-
rent transmit TDTE in host memory (TMD2), gives up
ownership (resets the OWN bit to 0) for this frame, and
processes the next frame in the transmit ring for trans-
mission.
Abnormal network conditions include:
Loss of carrier
Late collision
SQE Test Error (Does not apply to 100-Mbps net-
works.)
These conditions should not occur on a correctly con-
figured IEEE 802.3 network operating in half-duplex
mode. If they do, they will be reported. None of these
conditions will occur on a network operating in full-
duplex mode. (See the section
Full-Duplex Operation
for more detail.)
When an error occurs in the middle of a multi-buffer
frame transmission, the error status will be written in the
current descriptor. The OWN bit(s) in the subsequent
descriptor(s) will be cleared until the STP (the next
frame) is found.
Loss of Carrier
When operating in half-duplex mode, a loss of carrier
condition will be reported if the Am79C972 controller
cannot observe receive activity while it is transmitting
on the GPSI port.
When the MII port is selected, LCAR will be reported
for every frame transmitted if the controller detects a
loss of carrier.
Late Collision
A late collision will be reported if a collision condition
occurs after one slot time (512 bit times) after the trans-
mit process was initiated (first bit of preamble com-
menced). The Am79C972 controller will abandon the
transmit process for that frame, set Late Collision
(LCOL) in the associated TMD2, and process the next
transmit frame in the ring. Frames experiencing a late
collision will not be retried. Recovery from this condi-
tion must be performed by upper layer software.
SQE Test Error
In GPSI mode, CLSN must be asserted after the trans-
mission or otherwise CERR will be set. CERR will be
asserted in the 10BASE-T mode through the MII after
transmit, if the network port is in Link Fail state. CERR
will never cause INTA to be activated. It will, however,
set the ERR bit CSR0.
Receive Operation
The receive operation and features of the Am79C972
controller are controlled by programmable options. The
Am79C972 controller offers a large receive FIFO to
provide frame buffering for increased system latency,
automatic flushing of collision fragments (runt packets),
automatic receive pad stripping, and a variety of ad-
dress match options.
Receive Function Programming
Automatic pad field stripping is enabled by setting the
ASTRP_RCV bit in CSR4. This can provide flexibility in
the reception of messages using the IEEE 802.3 frame
format.
All receive frames can be accepted by setting the
PROM bit in CSR15. Acceptance of unicast and broad-
cast frames can be individually turned off by setting the
DRCVPA or DRCVBC bits in CSR15. The Physical Ad-
dress register (CSR12 to CSR14) stores the address
that the Am79C972 controller compares to the destina-
tion address of the incoming frame for a unicast ad-
dress match. The Logical Address Filter register
(CSR8 to CSR11) serves as a hash filter for multicast
address match.
The point at which the BMU will start to transfer data
from the receive FIFO to buffer memory is controlled by
the RCVFW bits in CSR80. The default established
during H_RESET is 01b, which sets the watermark flag
at 64 bytes filled.
For test purposes, the Am79C972 controller can be
programmed to accept runt packets by setting RPA in
CSR124.
Address Matching
The Am79C972 controller supports three types of ad-
dress matching: unicast, multicast, and broadcast. The
normal address matching procedure can be modified
by programming three bits in CSR15, the mode register
(PROM, DRCVPA, and DRCVBC).
If the first bit received after the SFD (the least signifi-
cant bit of the first byte of the destination address field)
is 0, the frame is unicast, which indicates that the frame
is meant to be received by a single node. If the first bit
received is 1, the frame is multicast, which indicates
that the frame is meant to be received by a group of
nodes. If the destination address field contains all 1s,
the frame is broadcast, which is a special type of multi-
cast. Frames with the broadcast address in the destina-
tion address field are meant to be received by all nodes
on the local area network.
When a unicast frame arrives at the Am79C972 con-
troller, the controller will accept the frame if the destina-
tion address field of the incoming frame exactly
matches the 6-byte station address stored in the Phys-
ical Address registers (PADR, CSR12 to CSR14). The
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| AM79C972BKC\\W | 制造商:Advanced Micro Devices 功能描述: |
| AM79C972BKC\W | 制造商:Advanced Micro Devices 功能描述: |
| AM79C972BKCW | 制造商:AMD 制造商全稱:Advanced Micro Devices 功能描述:PCnet⑩-FAST+ Enhanced 10/100 Mbps PCI Ethernet Controller with OnNow Support |
| AM79C972BKD/W | 制造商:Advanced Micro Devices 功能描述: |
| AM79C972BKD\\W | 制造商:Advanced Micro Devices 功能描述: |
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