參數(shù)資料
型號(hào): AM79C972
廠商: Advanced Micro Devices, Inc.
英文描述: PCnet⑩-FAST+ Enhanced 10/100 Mbps PCI Ethernet Controller with OnNow Support
中文描述: PCnet⑩與OnNow增強(qiáng)10/100 Mbps的快速以太網(wǎng)控制器支持的PCI
文件頁(yè)數(shù): 105/130頁(yè)
文件大?。?/td> 1580K
代理商: AM79C972
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Am79C972
105
8
PME_EN
PME
PME_EN enables the function to
assert PME. When a 0, PME as-
sertion is disabled.
Enable.
When
a
1,
This bit defaults to
0
if the func-
tion does not support PME gener-
ation from D3cold.
If the function supports PME from
D3cold, then this bit is sticky and
must be explicitly cleared by the
operating system each time the
operating system is initially load-
ed.
Read/write accessible always.
Sticky bit. This bit is reset by
POR. H_RESET, S_RESET, or
setting the STOP bit has no ef-
fect.
7-2
RES
Reserved locations. Read only.
1-0
PWR_STATE Power State. This 2-bit field is
used both to determine the cur-
rent power state of a function and
to set the function into a new
power state. The definition of the
field values is given below.
00b - D0.
01b - D1.
10b - D2.
11b - D3.
These bits can be written and
read, but their contents have no
effect on the operation of the de-
vice.
Read/write accessible always.
PCI PMCSR Bridge Support Extensions Register
Offset 46h
Bit
Name
Description
7-0
PMCSR_BSE The PCI PMCSR Bridge Support
Extensions Register is an 8-bit
register. PMCSR Bridge Support
Extensions are not supported.
This register has a default value
of 00h.
The PCI PMCSR Bridge Support
Extensions register is located at
offset 46h in the PCI Configura-
tion Space. It is read only.
PCI Data Register
Offset 47h
Note:
All bits of this register are loaded from EE-
PROM. The register is aliased to lower bytes of the
BCR37-44 for testing purposes.
Bit
Name
Description
7-0
DATA_REG The PCI Data Register is an 8-bit
register. Refer to the
PCI Bus
Power Management Interface
Specification
version 1.0 for a
more detailed description of this
register.
The PCI DATA register is located
at offset 47h in the PCI Configu-
ration Space. It is read only.
RAP Register
The RAP (Register Address Pointer) register is used to
gain access to CSR and BCR registers on board the
Am79C972 controller. The RAP contains the address
of a CSR or BCR.
As an example of RAP use, consider a read access to
CSR4. In order to access this register, it is necessary
to first load the value 0004h into the RAP by performing
a write access to the RAP offset of 12h (12h when WIO
mode has been selected, 14h when DWIO mode has
been selected). Then a second access is performed,
this time to the RDP offset of 10h (for either WIO or
DWIO mode). The RDP access is a read access, and
since RAP has just been loaded with the value of 0004h,
the RDP read will yield the contents of CSR4. A read of
the BDP at this time (offset of 16h when WIO mode has
been selected, 1Ch when DWIO mode has been select-
ed) will yield the contents of BCR4, since the RAP is
used as the pointer into both BDP and RDP space.
RAP: Register Address Port
Bit
Name
Description
31-16
RES
Reserved locations. Written as
zeros and read as undefined.
15-8
RES
Reserved locations. Read and
written as zeros.
7-0
RAP
Register Address Port. The value
of these 8 bits determines which
CSR or BCR will be accessed
when an I/O access to the RDP
or BDP port, respectively, is per-
formed.
A write access to undefined CSR
or BCR locations may cause un-
expected reprogramming of the
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