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參數(shù)資料
| 型號(hào)： | AM79C970AVCW |
| 廠商： | ADVANCED MICRO DEVICES INC |
| 元件分類(lèi)： | 微控制器/微處理器 |
| 英文描述： | PCnet-PCI II Single-Chip Full-Duplex Ethernet Controller for PCI Local Bus Product |
| 中文描述： | 2 CHANNEL(S), 10M bps, LOCAL AREA NETWORK CONTROLLER, PQFP144 |
| 封裝： | TQFP-144 |
| 文件頁(yè)數(shù)： | 91/219頁(yè) |
| 文件大小： | 1065K |
| 代理商： | AM79C970AVCW |
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P R E L I M I N A R Y
AMD
91
Am79C970A
19436A-42
PCnet–PCI II
EROE
ERACLK
ERA[7:0]
ERD[7:0]
Expansion ROM
CE
OE
A[15:8]
A[7:0]
D[7:0]
Latch
Figure 39. Expansion ROM Interface
The PCnet-PCI II controller will always read four bytes
for every host Expansion ROM read access. The inter-
face to the Expansion ROM runs synchronous to the
PCI bus interface clock. The PCnet-PCI II controller will
start the read operation to the Expansion ROM by driv-
ing the upper 8-bits of the Expansion ROM address on
ERA[7:0]. This happens in the same clock cycle that the
device claims the transfer by asserting
DEVSEL
. One
clock later,
EROE
is asserted and ERACLK goes high to
allow latching of the upper address bits externally. The
upper portion of the Expansion ROM address will be the
same for all four byte read cycles. ERACLK is asserted
for one clock. ERA[7:0] are driven with the upper 8-bits
of the Expansion ROM address for one more clock cycle
after ERACLK goes low. Next, the PCnet-PCI II control-
ler starts driving the lower 8 bits of the Expansion ROM
address on ERA[7:0].
The time the PCnet-PCI II controller waits for data to be
valid is programmable. ROMTMG (BCR18, bits 15–12)
defines the time from when the PCnet-PCI II controller
drives ERA[7:0] with the lower 8-bits of the Expansion
ROM address to when the PCnet-PCI II controller
latches in the data on the ERD[7:0] inputs. The register
value specifies the time in number of clock cycles. When
ROMTMG is set to Nine (the default value), ERD[7:0] is
sampled with the next rising edge of CLK nine clock cy-
cles after ERA[7:0] was driven with a new address
value. The clock edge that is used to sample the data is
also the clock edge that generates the next Expansion
ROM address. Only the first three bytes of Expansion
ROM data are stored in holding registers. The fourth
byte is passed directly from the ERD[7:0] inputs to the
AD[31:24] outputs. One clock cycle after the last data
byte is available, PCnet-PCI II controller asserts
TRDY
.
Two clock cycles after the data is transferred on the PCI
bus,
EROE
is deasserted.
The access time for the Expansion ROM device (t
ACC
)
can be calculated by subtracting the clock to output de-
lay for the ERA[7:0] outputs (t
VAL
(ERA)) and the input to
clock setup time for the ERD[7:0] inputs (t
SU
(ERD)) from
the time defined by ROMTMG:
t
ACC
≤
ROMTMG* clock period – t
VAL
(ERA) – t
SU
(ERD)
For an adapter card application, the value used for clock
period should be 30 ns to guarantee correct interface
timing at the maximum clock frequency of 33 MHz.
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| AM79C970AVI\\W | 制造商:Rochester Electronics LLC 功能描述:- Bulk |
| AM79C970AVI\W | 制造商:Rochester Electronics LLC 功能描述:- Bulk |
| AM79C970AVIW | 制造商:Rochester Electronics LLC 功能描述: |
| AM79C970AVW | 制造商:Rochester Electronics LLC 功能描述:- Bulk |
| AM79C970AWW WAF | 制造商:Advanced Micro Devices 功能描述: |
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