參數(shù)資料
型號(hào)： AM79C970AVCW
廠商： ADVANCED MICRO DEVICES INC
元件分類： 微控制器/微處理器
英文描述： PCnet-PCI II Single-Chip Full-Duplex Ethernet Controller for PCI Local Bus Product
中文描述： 2 CHANNEL(S), 10M bps, LOCAL AREA NETWORK CONTROLLER, PQFP144
封裝： TQFP-144
文件頁(yè)數(shù)： 156/219頁(yè)
文件大?。?/td> 1065K
代理商： AM79C970AVCW
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AMD
P R E L I M I N A R Y
156
Am79C970A
Table 33. EEDET Setting
EEDET
Value
(BCR19[3])
EEPROM
Connected
Result of Automatic EEPROM Read
Operation Following H_RESET
Result if PREAD is Set to ONE
0
No
EEPROM read operation is attempted.
Entire read sequence will occur,
checksum failure will result, PVALID
is cleared to ZERO.
First TWO EESK clock cycles are
generated, then EEPROM read
operation is aborted and PVALID
is cleared to ZERO.
0
Yes
EEPROM read operation is attempted.
Entire read sequence will occur,
checksum operation will pass, PVALID
is set to ONE.
First TWO EESK clock cycles are
generated, then EEPROM read
operation is aborted and PVALID is
cleared to ZERO.
1
No
EEPROM read operation is attempted.
Entire read sequence will occur,
checksum failure will result, PVALID
is cleared to ZERO.
EEPROM read operation is attempted.
Entire read sequence will occur,
checksum failure will result, PVALID is
cleared to ZERO.
1
Yes
EEPROM read operation is attempted.
Entire read sequence will occur,
checksum operation will pass, PVALID
is set to ONE.
EEPROM read operation is attempted.
Entire read sequence will occur,
checksum operation will pass, PVALID
is set to ONE.
12–5
RES
Reserved locations. Written as
ZEROs, read as undefined.
4
EEN
EEPROM port enable. When this
bit is set to ONE, it causes the
values of ECS, ESK, and EDI to
be driven onto the EECS, EESK,
and EEDI pins, respectively. If
EEN is cleared to ZERO and no
EEPROM
read
currently active, then EECS will
be driven LOW and the EESK
and EEDI pins change their
function to
LED1
and
LNKST
and
are controlled by BCR5 and
BCR4, respectively.
function
is
Read accessible always. Write
accessible only when either the
STOP or the SPND bit is set.
EEN is cleared to ZERO by
H_RESET and is unaffected by
S_RESET or by setting the
STOP bit.
3
RES
Reserved location. Written as
ZERO and read as undefined.
2
ECS
EEPROM Chip Select. This bit is
used to control the value of the
EECS pin of the Microwire inter-
face when the EEN bit is set to
ONE and the PREAD bit is
cleared to ZERO. If EEN is set to
ONE and PREAD is cleared to
ZERO and ECS is set to ONE,
then the EECS pin will be forced
to a HIGH level at the rising edge
of the next clock following bit pro-
gramming. If EEN is set to ONE
and PREAD is cleared to ZERO
and ECS is cleared to ZERO,
then the EECS pin will be forced
to a LOW level at the rising edge
of the next clock following bit pro-
gramming. ECS has no effect on
the output value of the EECS pin
unless the PREAD bit is cleared
to ZERO and the EEN bit is set
to ONE.
Read accessible always. Write
accessible only when either the
STOP or the SPND bit is set.
ECS is cleared to ZERO by
H_RESET and is not affected by
S_RESET or by setting the
STOP bit.
1
ESK
EEPROM Serial Clock. This bit
and the EDI/EDO bit are used to
control host access to the
EEPROM. Values programmed
to this bit are placed on to the
EESK pin at the rising edge of the
next clock following bit program-
ming, except when the PREAD
bit is set to ONE or the EEN bit is
cleared to ZERO. If both the ESK
bit and the EDI/EDO bit values
are changed during one BCR19
write operation while EEN is set
to ONE, then setup and hold
times of the EEDI pin value with
respect to the EESK signal edge
are not guaranteed.
ESK has no effect on the EESK
pin unless the PREAD bit is
cleared to ZERO and the EEN bit
is set to ONE.
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