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| 型號(hào)： | AM79C960KCW |
| 廠商： | ADVANCED MICRO DEVICES INC |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | PCnetTM-ISA Single-Chip Ethernet Controller |
| 中文描述： | 2 CHANNEL(S), 10M bps, LOCAL AREA NETWORK CONTROLLER, PQFP120 |
| 封裝： | PLASTIC, QFP-120 |
| 文件頁(yè)數(shù)： | 48/127頁(yè) |
| 文件大小： | 814K |
| 代理商： | AM79C960KCW |
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P R E L I M I N A R Y
AMD
1-390
Am79C960
Power Savings Modes
The PCnet-ISA controller supports two hardware
power-savings modes. Both are entered by asserting
the
SLEEP
pin LOW.
In
coma
mode, the PCnet-ISA controller will go into
deep sleep with no support to automatically wake itself
up. Coma mode is enabled when the AWAKE bit in
ISACSR2 is reset. This mode is the default power down
mode.
In
snooze
mode, enabled by setting the AWAKE bit in
ISACSR2 and driving the
SLEEP
pin LOW, the T-MAU
receive circuitry will remain enabled even while the
SLEEP
pin is driven LOW. The
LED0
output will also
continue to function, indicating a good 10BASE-T link if
there are link beat pulses or valid frames present. This
LED0
pin can be used to drive a LED and/or external
hardware that directly controls the
SLEEP
pin of the
PCnet-ISA controller. This configuration effectively
wakes the system when there is any activity on the
10BASE-T link.
Access Operations (Software)
We begin by describing how byte and word data are ad-
dressed on the ISA bus, including conversion cycles
where 16-bit accesses are turned into 8-bit accesses
because the resource accessed did not support 16-bit
operations. Then we describe how registers and other
resources are accessed. This section is for the device
programmer, while the next section (bus cycles) is for
the hardware designer.
I/O Resources
The PCnet-ISA controller has both I/O and memory re-
sources. In the I/O space the resources are organized
as indicated in the following table:
Offset
#Bytes
Register
0h
16
IEEE Address PROM
10h
2
RDP
12h
2
RAP(shared by RDP and IDP)
14h
2
Reset
16h
2
IDP
The PCnet-ISA controller does not respond to any ad-
dresses outside of the offset range 0-17h. I/O offsets
18h and up are not used by the PCnet-ISA controller.
I/O Register Access
The register address port (RAP) is shared by the regis-
ter data port (RDP) and the ISACSR data port (IDP) to
save registers. To access the Ethernet controller’s RDP
or IDP, the RAP should be written first, followed by the
read or write access to the RDP or IDP. I/O register ac-
cesses should be coded as 16-bit accesses, even if the
PCnet-ISA controller is hardware configured for 8-bit I/O
bus cycles. It is acceptable (and transparent) for the
motherboard to turn a 16-bit software access into two
separate 8-bit hardware bus cycles. The motherboard
accesses the low byte before the high byte and the
PCnet-ISA controller has circuitry to specifically support
this type of access.
The reset register causes a reset when read. Any value
will be accepted and the cycle may be 8 or 16 bits wide.
Writes are ignored.
All PCnet-ISA controller register accesses should be
coded as 16-bit operations.
*Note that the RAP is cleared on Reset.
Address PROM Access
The address PROM is an external memory device that
contains the node’s unique physical Ethernet address
and any other data stored by the board manufacturer.
The software accesses may be 8- or 16-bit.
Boot PROM Access
The boot PROM is an external memory resource lo-
cated at the address selected by the IOAM0 and IOAM1
pins in bus master mode, or the
BPAM
input in shared
memory mode. It may be software accessed as an 8- or
16-bit resource but the latter is recommended for best
performance.
Static RAM Access
The static RAM is only present in the shared memory
mode. It is located at the address selected by the
SMAM
input. It may be accessed as an 8- or 16-bit resource but
the latter is recommended for best performance.
Bus Cycles (Hardware)
The PCnet-ISA controller supports both 8- and 16-bit
hardware bus cycles. The following sections outline
where any limitations apply based upon the architecture
mode and/or the resource that is being accessed
(PCnet-ISA controller registers, address PROM, boot
PROM, or shared memory SRAM). For completeness,
the following sections are arranged by architecture (Bus
Master Mode or Shared Memory Mode). SRAM re-
sources apply only to Shared Memory Mode.
All resources (registers, PROMs, SRAM) are presented
to the ISA bus by the PCnet-ISA controller. With few ex-
ceptions, these resources can be configured for either
8-bit or 16-bit bus cycles. The I/O resources (registers,
address PROM) are width configured using the
IOCS16
pin on the PCnet-ISA controller. The memory resources
(boot PROM, SRAM) are width configured by external
hardware.
For 16-bit memory accesses, hardware external to the
PCnet-ISA controller asserts
MEMCS16
when either of
the two memory resources is selected. The ISA bus re-
quires that all memory resources within a block of
128 Kbytes be the same width, either 8- or 16-bits. The
reason for this is that the
MEMCS16
signal is generally
a decode of the LA
17-23
address lines. 16-bit memory
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相關(guān)代理商/技術(shù)參數(shù) |
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| AM79C961 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Am79C961 - PCnet-ISA+ Jumperless Single-Chip Ethernet Controller for ISA |
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| AM79C961A | 制造商:AMD 制造商全稱:Advanced Micro Devices 功能描述:PCnet⑩-ISA II Jumperless, Full Duplex Single-Chip Ethernet Controller for ISA |
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