參數(shù)資料
型號(hào)： AM79C940JCW
廠商： Advanced Micro Devices, Inc.
英文描述： Media Access Controller for Ethernet (MACE)
中文描述： 媒體訪問(wèn)控制器（MACE發(fā)生以太網(wǎng)）
文件頁(yè)數(shù)： 63/122頁(yè)
文件大?。?/td> 914K
代理商： AM79C940JCW
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AMD
63
Am79C940
the transmission of a packet and
updated the Transmit Frame
Status. The
INTR
pin will be acti-
vated if the corresponding mask
bit XMTINTM = 0.
XMTINT is READ/CLEAR only. It
is set by the MACE device and
reset when read. Writing has no
effect. It is also cleared by activa-
tion of the
RESET
pin or SWRST
bit.
Interrupt Mask Register (IMR)
This register contains the mask bits for the interrupts.
Read/write operations are permitted. Writing a one into
a bit will mask the corresponding interrupt. Writing a
zero to any previously set bit will unmask the corre-
sponding interrupt. Bit assignments for the register are
as follows:
(REG ADDR 9)
RES
CERRM RCVCCOM RNTPCOM
MPCOM
RCVINTM
BABLM
XMTINTM
Bit
Name
Description
Bit 7
JABM
Jabber Error Mask. JABM is the
mask for JAB. The
INTR
pin will
not be asserted by the MACE de-
vice regardless of the state of the
JAB bit, if JABM is set. It is
cleared by activation of the
RE-
SET
pin or SWRST bit.
Babble Error Mask. BABLM is
the mask for BABL. The
INTR
pin
will not be asserted by the MACE
device regardless of the state of
the BABL bit, if BABLM is set. It is
cleared by activation of the
RESET
pin or SWRST bit.
Collision Error Mask. CERRM is
the mask for CERR. The
INTR
pin will not be asserted by the
MACE device regardless of the
state of the CERR bit, if CERRM
is set. It is cleared by activation of
the
RESET
pin or SWRST bit.
RCVCCOM Receive Collision Count Over-
flow Mask. RCVCCOM is the
mask for RCVCCO(Receive Col-
lision Count Overflow). The
INTR
pin will not be asserted by the
MACE device regardless of the
state of the RCVCCO bit, if
RCVCCOM is set. It is cleared by
activation of the
RESET
pin or
SWRST bit.
Bit 6
BABLM
Bit 5
CERRM
Bit 4
Bit 3
RNTPCOM Runt Packet Count Overflow
Mask. RNTPCOM is the mask for
RNTPCO (Runt Packet Count
Overflow). The
INTR
pin will not
be asserted by the MACE device
regardless of the state of the
RNTPCO bit, if RNTPCOM is set.
It is cleared by activation of the
RESET
pin or SWRST bit.
MPCOM
Missed Packet Count Overflow
Mask. MPCOM is the mask for
MPCO (Missed Packet Count
Overflow). The
INTR
pin will not
be asserted by the MACE device
regardless of the state of the
MPCO bit, if MPCOM is set. It is
cleared by activation of the
RESET
pin or SWRST bit.
RCVINTM
Receive
RCVINTM is the mask for
RCVINT. The
INTR
pin will not be
asserted by the MACE device re-
gardless of the state of the
RCVINT bit, if RCVINTM is set. It
is cleared by activation of the
RESET
pin or SWRST bit.
XMTINTM
Transmit
XMTINTM is the mask for
XMTINT. The
INTR
pin will not be
asserted by the MACE device re-
gardless of the state of the
XMTINT bit, if XMTINT is set. It is
cleared by activation of the
RE-
SET
pin or SWRST bit.
Bit 2
Bit 1
Interrupt
Mask.
Bit 0
Interrupt
Mask.
Poll Register (PR)
This register contains copies of internal status bits to
simplify a host implementation which is non-interrupt
driven. The register is read only, and its status is unaf-
fected by read operations. All register bits are cleared by
hardware or software reset. Bit assignments are as fol-
lows:
(REG ADDR 10)
XMTSV
TDTREQ
RDTREQ
RES
RES
RES
RES
RES
Bit
Name
Description
Bit 7
XMTSV
Transmit Status Valid. Transmit
Status Valid indicates that the
Transmit Frame Status is valid.
Transmit Data Transfer Request.
An internal indication of the cur-
rent request status of the Trans-
mit FIFO. TDTREQ is set when
the external
TDTREQ
signal is
asserted.
Bit 6
TDTREQ
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