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參數(shù)資料
| 型號： | AM79761 |
| 廠商： | Advanced Micro Devices, Inc. |
| 英文描述： | Physical Layer 10-Bit Transceiver for Gigabit Ethernet (GigaPHY⑩-SD) |
| 中文描述： | 物理層10位千兆以太網(wǎng)收發(fā)器（GigaPHY⑩，標清） |
| 文件頁數(shù)： | 15/20頁 |
| 文件大小： | 132K |
| 代理商： | AM79761 |
Am79761
15
P R E L I M I N A R Y
AC CHARACTERISTICS (Continued)
Figure 22.
Receive Timing Waveform
Table 22.
Receive AC Characteristics
Symbol
Parameter Description
Test Conditions
Min
Max
Unit
T
1
Data or COM_DET Valid prior
to RCLK/RCLKN rise
Measured between the 1.4 V
point of RCLK or RCLKN and a
valid level of RXD[0:9]. All
outputs driving 10 pF load.
3.0
—
ns
T
2
Data or COM_DET Valid after
RCLK or RCLKN rise
2.0
—
ns
T
3
Deviation of RCLK rising edge
to RCLKN rising edge delay
from nominal.
f
10
Nominal delay is 10 bit times.
Tested on sample basis
-500
500
ps
T
4
Deviation of RCLK, RCLKN
frequency from nominal.
f
-------------------
=
Whether or not locked to serial
data
-1.0
1.0
%
T
R
, T
F
RXD[0:9], COM_DET, RCLK,
RCLKN rise and fall time
Between V
IL(MAX)
and V
IH(MIN)
,
into 10 pf load.
—
2.4
ns
R
lat
Latency from RX
±
to RXD[0:9]
bc = Bit clock
ns = Nano second
15 bc + 2 ns
34 bc + 2 ns
—
T
LOCK
Data acquisition lock time @
1.25 Gbps
8B/10B IDLE pattern.
Tested on a sample basis
—
2.0
μ
s
Receive Data
Jitter
Receive Data Jitter Power
dBc, RMS for 10
-12
Bit Error
Ratio Tested on a sample basis
—
40
ps
T
1
T
2
RCLK
RCLKN
RXD[0:9]
Data Valid
Data Valid
Data Valid
T
3
T
4
21560A-8
delay
-----------
T
3
±
=
f
RCLK
2
T
4
±
PhaseNoise
100KHz
BitTime
∫
×
2
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