- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄366548 > Am7968-125LMC (Advanced Micro Devices, Inc.) TAXIchip Integrated Circuits(Transparent Asynchronous Xmitter-Receiver Interface) PDF資料下載
參數(shù)資料
| 型號(hào)： | Am7968-125LMC |
| 廠商： | Advanced Micro Devices, Inc. |
| 英文描述： | TAXIchip Integrated Circuits(Transparent Asynchronous Xmitter-Receiver Interface) |
| 中文描述： | TAXIchip集成電路（透明異步Xmitter，接收器接口） |
| 文件頁(yè)數(shù)： | 91/127頁(yè) |
| 文件大?。?/td> | 730K |
| 代理商： | AM7968-125LMC |
第1頁(yè)第2頁(yè)第3頁(yè)第4頁(yè)第5頁(yè)第6頁(yè)第7頁(yè)第8頁(yè)第9頁(yè)第10頁(yè)第11頁(yè)第12頁(yè)第13頁(yè)第14頁(yè)第15頁(yè)第16頁(yè)第17頁(yè)第18頁(yè)第19頁(yè)第20頁(yè)第21頁(yè)第22頁(yè)第23頁(yè)第24頁(yè)第25頁(yè)第26頁(yè)第27頁(yè)第28頁(yè)第29頁(yè)第30頁(yè)第31頁(yè)第32頁(yè)第33頁(yè)第34頁(yè)第35頁(yè)第36頁(yè)第37頁(yè)第38頁(yè)第39頁(yè)第40頁(yè)第41頁(yè)第42頁(yè)第43頁(yè)第44頁(yè)第45頁(yè)第46頁(yè)第47頁(yè)第48頁(yè)第49頁(yè)第50頁(yè)第51頁(yè)第52頁(yè)第53頁(yè)第54頁(yè)第55頁(yè)第56頁(yè)第57頁(yè)第58頁(yè)第59頁(yè)第60頁(yè)第61頁(yè)第62頁(yè)第63頁(yè)第64頁(yè)第65頁(yè)第66頁(yè)第67頁(yè)第68頁(yè)第69頁(yè)第70頁(yè)第71頁(yè)第72頁(yè)第73頁(yè)第74頁(yè)第75頁(yè)第76頁(yè)第77頁(yè)第78頁(yè)第79頁(yè)第80頁(yè)第81頁(yè)第82頁(yè)第83頁(yè)第84頁(yè)第85頁(yè)第86頁(yè)第87頁(yè)第88頁(yè)第89頁(yè)第90頁(yè)當(dāng)前第91頁(yè)第92頁(yè)第93頁(yè)第94頁(yè)第95頁(yè)第96頁(yè)第97頁(yè)第98頁(yè)第99頁(yè)第100頁(yè)第101頁(yè)第102頁(yè)第103頁(yè)第104頁(yè)第105頁(yè)第106頁(yè)第107頁(yè)第108頁(yè)第109頁(yè)第110頁(yè)第111頁(yè)第112頁(yè)第113頁(yè)第114頁(yè)第115頁(yè)第116頁(yè)第117頁(yè)第118頁(yè)第119頁(yè)第120頁(yè)第121頁(yè)第122頁(yè)第123頁(yè)第124頁(yè)第125頁(yè)第126頁(yè)第127頁(yè)
AMD
87
TAXIchip Integrated Circuits Technical Manual
The serial link will operate in the 40 to 175 MHz range as determined by the byte rate
clock, but the byte data rate will be determined by how often the user strobes the TAXI
Transmitter. The transmission speed is transparent to the user.
Some applications may have a serial link bandwidth limitation. Typically, this means that
the media connecting the Transmitter to the Receiver can only handle serial data rates
that are lower than 40 MHz. The user can run the TAXlchips in Test Mode in order to
overcome the 40 MHz lower frequency limitation.
For convenience in the following discussions, encoded data width nhas been set to 10,
corresponding to an 8-bit input byte, (i.e. DMS = LOW).
Since the multiplying PLL is turned off in Test Mode, an external clock source must be
supplied to the TAXls. In normal (non-test) mode, the Transmitter PLL multiplies the
byteclock by 10. The new 10X clock is called the bit clock or bitclk and is used to
transmit the serial data. The Receiver PLL generates the same type of bitclkto decode
the incoming data and to track and follow any fluctuations in the transmission frequency
of the incoming data.
In test mode the Transmitter PLL is disconnected and the internal clock multiplier is
switched out. The internal logic is now clocked directly by the signal applied to the CLK
pin. The input to the CLK pin now becomes the bitclk and must be supplied by the user.
On the Receiver side, the internal data tracking PLL is disconnected in Test Mode. An
external clock recovery circuit must be used to allow the Receiver to track the incoming
serial data stream. This recovered bitclk is supplied to X1. Either a digital PLL or an
analog PLL (for faster rates) can be used for clock recovery as shown in Figure 8-2.
The Transmitter and Receiver Test Mode connections and functionality are given in the
following section.
8.1 T ransmitter Connec tions
Refer to Figure 8-1.
The TLS pin is left floating. This is the pin that puts the Transmitter in Test Mode.
The
RESET
pin is left floating.
RESET
pin function is described in Appendix C, TAXI TIP
#89-02. The X2 pin is grounded.
SERIN is left floating (D/C = Do Not Connect).
The DMS pin is set in the appropriate state for 8-, 9- or 10-bit mode as desired by the
user.
The CLK is now an input for bitclk (the bit rate clock). This means that if the serial
transmission rate is to be 1.5 Kbits/s, CLK must be 1.5 kHz.
The ACK pin is raised only when a Sync byte is detected in the Transmitter’s shifter
latch (note that if STRB is lowered before ACK is seen, ACK will be suppressed. See the
STRB/ACK description in Section 7.1).
The X1 input is the reset pin for the internal state machines and can be left unconnected
in operational systems. For testing purposes, the following steps are to be taken upon
power up or initialization.
1. X1 should be kept HIGH and the Transmitter bitclked about 15 times
2. X1 should be lowered and the Transmitter bitclked about 200 times.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| AM7968-175DC | TAXIchip Integrated Circuits(Transparent Asynchronous Xmitter-Receiver Interface) |
| Am7968-175DMC | TAXIchip Integrated Circuits(Transparent Asynchronous Xmitter-Receiver Interface) |
| Am7968-175LMC | TAXIchip Integrated Circuits(Transparent Asynchronous Xmitter-Receiver Interface) |
| Am7969 | TAXIchip Integrated Circuits(Transparent Asynchronous Xmitter-Receiver Interface) |
| Am7968-125DKC | TAXIchip Integrated Circuits(Transparent Asynchronous Xmitter-Receiver Interface) |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| AM7968-125PC | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Transmitter |
| AM7968-125PCB | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Transmitter |
| AM7968-125VB3A | 制造商:AMD 制造商全稱:Advanced Micro Devices 功能描述:TAXIchip Integrated Circuits(Transparent Asynchronous Xmitter-Receiver Interface) |
| AM7968-125VBXA | 制造商:AMD 制造商全稱:Advanced Micro Devices 功能描述:TAXIchip Integrated Circuits(Transparent Asynchronous Xmitter-Receiver Interface) |
| AM7968-175DC | 制造商:Rochester Electronics LLC 功能描述: |
發(fā)布緊急采購(gòu)，3分鐘左右您將得到回復(fù)。