- 您現(xiàn)在的位置：買(mǎi)賣(mài)IC網(wǎng) > PDF目錄366548 > Am7968-125DKC (Advanced Micro Devices, Inc.) TAXIchip Integrated Circuits(Transparent Asynchronous Xmitter-Receiver Interface) PDF資料下載
參數(shù)資料
| 型號(hào)： | Am7968-125DKC |
| 廠商： | Advanced Micro Devices, Inc. |
| 英文描述： | TAXIchip Integrated Circuits(Transparent Asynchronous Xmitter-Receiver Interface) |
| 中文描述： | TAXIchip集成電路（透明異步Xmitter，接收器接口） |
| 文件頁(yè)數(shù)： | 114/127頁(yè) |
| 文件大?。?/td> | 730K |
| 代理商： | AM7968-125DKC |
第1頁(yè)第2頁(yè)第3頁(yè)第4頁(yè)第5頁(yè)第6頁(yè)第7頁(yè)第8頁(yè)第9頁(yè)第10頁(yè)第11頁(yè)第12頁(yè)第13頁(yè)第14頁(yè)第15頁(yè)第16頁(yè)第17頁(yè)第18頁(yè)第19頁(yè)第20頁(yè)第21頁(yè)第22頁(yè)第23頁(yè)第24頁(yè)第25頁(yè)第26頁(yè)第27頁(yè)第28頁(yè)第29頁(yè)第30頁(yè)第31頁(yè)第32頁(yè)第33頁(yè)第34頁(yè)第35頁(yè)第36頁(yè)第37頁(yè)第38頁(yè)第39頁(yè)第40頁(yè)第41頁(yè)第42頁(yè)第43頁(yè)第44頁(yè)第45頁(yè)第46頁(yè)第47頁(yè)第48頁(yè)第49頁(yè)第50頁(yè)第51頁(yè)第52頁(yè)第53頁(yè)第54頁(yè)第55頁(yè)第56頁(yè)第57頁(yè)第58頁(yè)第59頁(yè)第60頁(yè)第61頁(yè)第62頁(yè)第63頁(yè)第64頁(yè)第65頁(yè)第66頁(yè)第67頁(yè)第68頁(yè)第69頁(yè)第70頁(yè)第71頁(yè)第72頁(yè)第73頁(yè)第74頁(yè)第75頁(yè)第76頁(yè)第77頁(yè)第78頁(yè)第79頁(yè)第80頁(yè)第81頁(yè)第82頁(yè)第83頁(yè)第84頁(yè)第85頁(yè)第86頁(yè)第87頁(yè)第88頁(yè)第89頁(yè)第90頁(yè)第91頁(yè)第92頁(yè)第93頁(yè)第94頁(yè)第95頁(yè)第96頁(yè)第97頁(yè)第98頁(yè)第99頁(yè)第100頁(yè)第101頁(yè)第102頁(yè)第103頁(yè)第104頁(yè)第105頁(yè)第106頁(yè)第107頁(yè)第108頁(yè)第109頁(yè)第110頁(yè)第111頁(yè)第112頁(yè)第113頁(yè)當(dāng)前第114頁(yè)第115頁(yè)第116頁(yè)第117頁(yè)第118頁(yè)第119頁(yè)第120頁(yè)第121頁(yè)第122頁(yè)第123頁(yè)第124頁(yè)第125頁(yè)第126頁(yè)第127頁(yè)
AMD
110
TAXIchip Integrated Circuits Technical Manual
TAXI T
echnical
I
nformation
P
ublication
#89-13
S ubjec t: Demuxing A T AX Ic hip Rec eiver Output to Multi-Byte Words
Question:
How can a single TAXI Receiver be used to receive multi-byte words
Answer:
INT RODUCT ION
For systems that require data reception wider than a single byte, a single TAXI Receiver
can be used to cascade the multiple bytes. This operation allows the data to be
demultiplexed from a single serial link and used by an external system.
In the following example, data is captured sequentially and output in the form of four
8-bit words. Commands, which can also be transmitted are not used in this example in
order to clarify the basics of the technique. Some simple modifications to include
commands will be presented at the end of this technical note.
The circuit shown in Figure 14 illustrates the logic configuration that has been built and
tested in the laboratory using nominal commercial parts. The circuit handles blocks of
data typically ranging from four bytes to 64K bytes.
The TAXI Receiver converts the serial information that is received by the SERIN+/–
inputs to the data information that is output by the D0–D7 Data pins, C0–C3 Command
pins, and the DSTRB, CSTRB, and VLTN pins. This data information output by the
single receiver is used by the controllerto capture the incoming data and output it four
bytes at a time.
FUNCT IONAL DES CRIPT ION
Controller Circ uit:
The controllerconsists of a shift register constructed of four D flip-flops and a 3-input
NOR gate. The shifter is loaded with a 1that progresses through the flip-flops sequen-
tially clocking the first column of four registers which capture the incoming data. When
the 1is shifted through the fourth flip-flop, it raises the PCO signal for the CLKOUT D
flip-flop. On the following rising edge of the /CLK signal the bytes of cascaded data are
simultaneously clocked out through the second column of four registers that buffer the
cascaded data to the outside system.
Controller Cloc k:
The clock for the controllercircuit is generated by OR-ing DSTRB and CSTRB. This
ensures that the DSTRB signal is captured for output to the external system. These signals
also prepare the way for a simple upgrade to allow the use of commands (explained later).
S ync Commands:
When not receiving blocks of data, Sync Commands (bytes) are received which keeps
the TAXI Receiver locked onto the correct byte rate and byte boundaries. This ensures
proper capture of the data at the beginning of the next block. In addition, before a block
of data is to be sent, a Sync Command must be received to reset the counter to the
proper byte alignment and initialize the system. The Sync Commands are sent by
default in the system because they are automatically inserted whenever a byte time
passes without a STRB (no data to send) pulse at the transmitter. It is important to note
that the Receiver generates a CSTRB and outputs zeros on the Command lines when a
Sync Command is received.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| Am7969-125DKC | TAXIchip Integrated Circuits(Transparent Asynchronous Xmitter-Receiver Interface) |
| Am7968-175DKC | TAXIchip Integrated Circuits(Transparent Asynchronous Xmitter-Receiver Interface) |
| Am7969-175DKC | TAXIchip Integrated Circuits(Transparent Asynchronous Xmitter-Receiver Interface) |
| Am7969-125 | TAXIchip Integrated Circuits(Transparent Asynchronous Xmitter-Receiver Interface) |
| AM7969-125DC | TAXIchip Integrated Circuits(Transparent Asynchronous Xmitter-Receiver Interface) |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| AM7968-125DMC | 制造商:AMD 制造商全稱(chēng):Advanced Micro Devices 功能描述:TAXIchip Integrated Circuits(Transparent Asynchronous Xmitter-Receiver Interface) |
| AM7968-125JC | 制造商:Advanced Micro Devices 功能描述: 制造商:Rochester Electronics LLC 功能描述: |
| AM7968-125JCB | 制造商:未知廠家 制造商全稱(chēng):未知廠家 功能描述:Transmitter |
| AM7968-125JC-G | 制造商:Rochester Electronics LLC 功能描述:- Bulk |
| AM7968-125LE | 制造商:未知廠家 制造商全稱(chēng):未知廠家 功能描述:Transmitter |
發(fā)布緊急采購(gòu)，3分鐘左右您將得到回復(fù)。