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參數(shù)資料
| 型號： | AM75PDL193CHHA70I |
| 廠商： | SPANSION LLC |
| 元件分類： | 存儲器 |
| 英文描述： | 128 Megabit (8 M x 16-Bit) CMOS 3.0 Volt-only, Simultaneous Read/Write Flash Memory |
| 中文描述： | SPECIALTY MEMORY CIRCUIT, PBGA73 |
| 封裝： | 9 X 13 MM, FBGA-73 |
| 文件頁數(shù)： | 83/129頁 |
| 文件大?。?/td> | 852K |
| 代理商： | AM75PDL193CHHA70I |
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January 14, 2004
Am75PDL191CHHa/Am75PDL193CHHa
81
A D V A N C E I N F O R M A T I O N
dresses are changed. While in sleep mode, output
data is latched and always available to the system.
I
CC5
in the DC Characteristics table represents the
automatic sleep mode current specification.
RESET#: Hardware Reset Pin
The RESET# pin provides a hardware method of re-
setting the device to reading array data. When the RE-
SET# pin is driven low for at least a period of t
RP
, the
device immediately terminates any operation in
progress, tristates all output pins, and ignores all
read/write commands for the duration of the RESET#
pulse. The device also resets the internal state ma-
chine to reading array data. The operation that was in-
terrupted should be reinitiated once the device is
ready to accept another command sequence, to en-
sure data integrity.
Current is reduced for the duration of the RESET#
pulse. When RESET# is held at V
SS
±0.3 V, the device
draws CMOS standby current (I
CC4
). If RESET# is held
at V
IL
but not within V
SS
±0.3 V, the standby current will
be greater.
The RESET# pin may be tied to the system reset cir-
cuitry. A system reset would thus also reset the Flash
memory, enabling the system to read the boot-up firm-
ware from the Flash memory.
If RESET# is asserted during a program or erase op-
eration, the RY/BY# pin remains a “0” (busy) until the
internal reset operation is complete, which requires a
time of t
READY
(during Embedded Algorithms). The sys-
tem can thus monitor RY/BY# to determine whether
the reset operation is complete. If RESET# is asserted
when a program or erase operation is not executing
(RY/BY# pin is “1”), the reset operation is completed
within a time of t
READY
(not during Embedded Algo-
rithms). The system can read data t
RH
after the RE-
SET# pin returns to V
IH
.
Refer to the pSRAM AC Characteristics tables for RE-
SET# parameters and to Figure 15 for the timing dia-
gram.
Output Disable Mode
When the OE# input is at V
IH
, output from the device is
disabled. The output pins are placed in the high
impedance state.
Table 2.
Am29DL640H Sector Architecture
Bank
Sector
Sector Address
A21–A12
0000000000
0000000001
0000000010
0000000011
0000000100
0000000101
0000000110
0000000111
0000001xxx
0000010xxx
0000011xxx
0000100xxx
0000101xxx
0000110xxx
0000111xxx
0001000xxx
0001001xxx
0001010xxx
0001011xxx
0001100xxx
0001101xxx
0001101xxx
0001111xxx
Sector Size
(Kwords)
4
4
4
4
4
4
4
4
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
(x16)
Address Range
00000h–00FFFh
01000h–01FFFh
02000h–02FFFh
03000h–03FFFh
04000h–04FFFh
05000h–05FFFh
06000h–06FFFh
07000h–07FFFh
08000h–0FFFFh
10000h–17FFFh
18000h–1FFFFh
20000h–27FFFh
28000h–2FFFFh
30000h–37FFFh
38000h–3FFFFh
40000h–47FFFh
48000h–4FFFFh
50000h–57FFFh
58000h–5FFFFh
60000h–67FFFh
68000h–6FFFFh
70000h–77FFFh
78000h–7FFFFh
Bank 1
SA0
SA1
SA2
SA3
SA4
SA5
SA6
SA7
SA8
SA9
SA10
SA11
SA12
SA13
SA14
SA15
SA16
SA17
SA18
SA19
SA20
SA21
SA22
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| Am75PDL191CHH | 128 Megabit (8 M x 16-Bit) CMOS 3.0 Volt-only, Simultaneous Read/Write Flash Memory |
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| AM75PDL191CHH70I | 128 Megabit (8 M x 16-Bit) CMOS 3.0 Volt-only, Simultaneous Read/Write Flash Memory |
| Am75PDL193CHH | 128 Megabit (8 M x 16-Bit) CMOS 3.0 Volt-only, Simultaneous Read/Write Flash Memory |
| AM75PDL193CHH70I | 128 Megabit (8 M x 16-Bit) CMOS 3.0 Volt-only, Simultaneous Read/Write Flash Memory |
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