參數(shù)資料
型號(hào)： AM75PDL193CHHA70I
廠商： SPANSION LLC
元件分類： 存儲(chǔ)器
英文描述： 128 Megabit (8 M x 16-Bit) CMOS 3.0 Volt-only, Simultaneous Read/Write Flash Memory
中文描述： SPECIALTY MEMORY CIRCUIT, PBGA73
封裝： 9 X 13 MM, FBGA-73
文件頁數(shù)： 81/129頁
文件大?。?/td> 852K
代理商： AM75PDL193CHHA70I
January 14, 2004
Am75PDL191CHHa/Am75PDL193CHHa
79
A D V A N C E I N F O R M A T I O N
DEVICE BUS OPERATIONS
This section describes the requirements and use of
the device bus operations, which are initiated through
the internal command register. The command register
itself does not occupy any addressable memory loca-
tion. The register is a latch used to store the com-
mands, along with the address and data information
needed to execute the command. The contents of the
register serve as inputs to the internal state machine.
The state machine outputs dictate the function of the
device. Table 1 lists the device bus operations, the in-
puts and control levels they require, and the resulting
output. The following subsections describe each of
these operations in further detail.
Table 1.
Am29DL640H Device Bus Operations
Legend:
L = Logic Low = V
IL
, H = Logic High = V
IH
, V
ID
= 11.5–12.5 V, V
HH
= 9.0 ± 0.5 V, X = Don’t Care, SA = Sector Address,
A
IN
= Address In, D
IN
= Data In, D
OUT
= Data Out
Notes:
1. Addresses are A21:A0 in word mode.
2. The sector protect and sector unprotect functions may also be implemented via programming equipment. See the “Sector/Sector
Block Protection and Unprotection” section.
3. If WP#/ACC = V
IL
, sectors 0, 1, 140, and 141 remain protected. If WP#/ACC = V
IH
, protection on sectors 0, 1, 140, and 141
depends on whether they were last protected or unprotected using the method described in “Sector/Sector Block Protection
and Unprotection”. If WP#/ACC = V
HH
, all sectors will be unprotected.
Word/Byte Configuration
The BYTE# pin controls whether the device data I/O
pins operate in the byte or word configuration. If the
BYTE# pin is set at logic ‘1’, the device is in word con-
figuration, DQ15–DQ0 are active and controlled by
CE# and OE#.
If the BYTE# pin is set at logic ‘0’, the device is in byte
configuration, and only data I/O pins DQ7–DQ0 are
active and controlled by CE# and OE#. The data I/O
pins DQ14–DQ8 are tri-stated, and the DQ15 pin is
used as an input for the LSB (A-1) address function.
Requirements for Reading Array Data
To read array data from the outputs, the system must
drive the CE# and OE# pins to V
IL
. CE# is the power
control and selects the device. OE# is the output con-
trol and gates array data to the output pins. WE#
should remain at V
IH
. The BYTE# pin determines
whether the device outputs array data in words or
bytes.
The internal state machine is set for reading array data
upon device power-up, or after a hardware reset. This
ensures that no spurious alteration of the memory
content occurs during the power transition. No com-
mand is necessary in this mode to obtain array data.
Standard microprocessor read cycles that assert valid
addresses on the device address inputs produce valid
data on the device data outputs. Each bank remains
enabled for read access until the command register
contents are altered.
Operation
CE#
OE#
WE#
RESET#
WP#/ACC
Addresses
(Note 2)
DQ15–DQ8
DQ7–
DQ0
Read
L
L
H
H
L/H
A
IN
D
OUT
D
OUT
Write
L
H
L
H
(Note 3)
A
IN
D
IN
D
IN
Standby
V
CC
±
0.3 V
X
X
V
CC
±
0.3 V
L/H
X
High-Z
High-Z
Output Disable
L
H
H
H
L/H
X
High-Z
High-Z
Reset
X
X
X
L
L/H
X
High-Z
High-Z
Sector Protect (Note 2)
L
H
L
V
ID
L/H
SA, A6 = L,
A1 = H, A0 = L
X
D
IN
Sector Unprotect (Note 2)
L
H
L
V
ID
(Note 3)
SA, A6 = H,
A1 = H, A0 = L
X
D
IN
Temporary Sector
Unprotect
X
X
X
V
ID
(Note 3)
A
IN
D
IN
D
IN
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