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參數(shù)資料
| 型號： | AM70PDL9BDH85IT |
| 廠商： | Spansion Inc. |
| 英文描述： | Stacked Multi-Chip Package (MCP/XIP) Flash Memory, Data storage MirrorBit Flash, and pSRAM (XIP) |
| 中文描述： | 堆疊式多芯片封裝（MCP / XIP）的快閃記憶體，數(shù)據(jù)存儲的MirrorBit閃存和移動存儲芯片（XIP）的 |
| 文件頁數(shù)： | 93/128頁 |
| 文件大小： | 916K |
| 代理商： | AM70PDL9BDH85IT |
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November 25, 2003
Am70PDL127BDH/Am70PDL129BDH
91
A D V A N C E I N F O R M A T I O N
Hardware Data Protection
The command sequence requirement of unlock cycles
for programming or erasing provides data protection
against inadvertent writes (refer to Tables
10
and
11
for command definitions). In addition, the following
hardware data protection measures prevent accidental
erasure or programming, which might otherwise be
caused by spurious system level signals during V
CC
power-up and power-down transitions, or from system
noise.
Low V
CC
Write Inhibit
When V
CC
is less than V
LKO
, the device does not ac-
cept any write cycles. This protects data during V
CC
power-up and power-down. The command register
and all internal program/erase circuits are disabled,
and the device resets to the read mode. Subsequent
writes are ignored until V
CC
is greater than V
LKO
. The
system must provide the proper signals to the control
pins to prevent unintentional writes when V
CC
is
greater than V
LKO
.
Write Pulse “Glitch” Protection
Noise pulses of less than 5 ns (typical) on OE#, CE#
or WE# do not initiate a write cycle.
Logical Inhibit
Write cycles are inhibited by holding any one of OE# =
V
IL
, CE# = V
IH
or WE# = V
IH
. To initiate a write cycle,
CE# and WE# must be a logical zero while OE# is a
logical one.
Power-Up Write Inhibit
If WE# = CE# = V
IL
and OE# = V
IH
during power up,
the device does not accept commands on the rising
edge of WE#. The internal state machine is automati-
cally reset to the read mode on power-up.
COMMON FLASH MEMORY INTERFACE (CFI)
The Common Flash Interface (CFI) specification out-
lines device and host system software interrogation
handshake, which allows specific vendor-specified
software algorithms to be used for entire families of
devices. Software support can then be device-inde-
pendent, JEDEC ID-independent, and forward- and
backward-compatible for the specified flash device
families. Flash vendors can standardize their existing
interfaces for long-term compatibility.
This device enters the CFI Query mode when the sys-
tem writes the CFI Query command, 98h, to address
55h, any time the device is ready to read array data.
The system can read CFI information at the addresses
given in Tables
6
–
9
. To terminate reading CFI data,
the system must write the reset command.
The system can also write the CFI query command
when the device is in the autoselect mode. The device
enters the CFI query mode, and the system can read
CFI data at the addresses given in Tables
6
–
9
. The
system must write the reset command to return the
device to reading array data.
For further information, please refer to the CFI Specifi-
cation and CFI Publication 100, available via the World
Wide Web at http://www.amd.com/flash/cfi. Alterna-
tively, contact an AMD representative for copies of
these documents.
Table 5.
CFI Query Identification String
Addresses
(x16)
Data
Description
10h
11h
12h
0051h
0052h
0059h
Query Unique ASCII string “QRY”
13h
14h
0002h
0000h
Primary OEM Command Set
15h
16h
0040h
0000h
Address for Primary Extended Table
17h
18h
0000h
0000h
Alternate OEM Command Set (00h = none exists)
19h
1Ah
0000h
0000h
Address for Alternate OEM Extended Table (00h = none exists)
相關PDF資料 |
PDF描述 |
|---|---|
| AM70PDLI27BDH | Stacked Multi-Chip Package (MCP/XIP) Flash Memory, Data storage MirrorBit Flash, and pSRAM (XIP) |
| AM70PDL127BDH85IT | 2 x 64 Megabit (8 M x 16-Bit) CMOS 3.0 Volt-Only Page Mode Flash Memory Data Storage 128 Megabit (8 M x 16-Bit) CMOS |
| AM70PDL127BDH | 2 x 64 Megabit (8 M x 16-Bit) CMOS 3.0 Volt-Only Page Mode Flash Memory Data Storage 128 Megabit (8 M x 16-Bit) CMOS |
| AM70PDL127BDH66IS | 2 x 64 Megabit (8 M x 16-Bit) CMOS 3.0 Volt-Only Page Mode Flash Memory Data Storage 128 Megabit (8 M x 16-Bit) CMOS |
| AM70PDL127BDH66IT | 2 x 64 Megabit (8 M x 16-Bit) CMOS 3.0 Volt-Only Page Mode Flash Memory Data Storage 128 Megabit (8 M x 16-Bit) CMOS |
相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| AM70PDLI27BDH | 制造商:SPANSION 制造商全稱:SPANSION 功能描述:Stacked Multi-Chip Package (MCP/XIP) Flash Memory, Data storage MirrorBit Flash, and pSRAM (XIP) |
| AM71000 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:ASIC |
| AM7100N | 制造商:ANALOGPOWER 制造商全稱:ANALOGPOWER 功能描述:N-Channel 100-V (D-S) MOSFET |
| AM7101P | 制造商:ANALOGPOWER 制造商全稱:ANALOGPOWER 功能描述:P-Channel 100-V (D-S) MOSFET |
| AM7102NA | 制造商:ANALOGPOWER 制造商全稱:ANALOGPOWER 功能描述:N-Channel 100-V (D-S) MOSFET |
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