參數(shù)資料
型號(hào)： AM70PDL9BDH85IT
廠商： Spansion Inc.
英文描述： Stacked Multi-Chip Package (MCP/XIP) Flash Memory, Data storage MirrorBit Flash, and pSRAM (XIP)
中文描述： 堆疊式多芯片封裝（MCP / XIP）的快閃記憶體，數(shù)據(jù)存儲(chǔ)的MirrorBit閃存和移動(dòng)存儲(chǔ)芯片（XIP）的
文件頁(yè)數(shù)： 83/128頁(yè)
文件大?。?/td> 916K
代理商： AM70PDL9BDH85IT
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November 25, 2003
Am70PDL127BDH/Am70PDL129BDH
81
A D V A N C E I N F O R M A T I O N
DEVICE BUS OPERATIONS
This section describes the requirements and use of
the device bus operations, which are initiated through
the internal command register. The command register
itself does not occupy any addressable memory loca-
tion. The register is a latch used to store the com-
mands, along with the address and data information
needed to execute the command. The contents of the
register serve as inputs to the internal state machine.
The state machine outputs dictate the function of the
device.
Table 1
lists the device bus operations, the in-
puts and control levels they require, and the resulting
output. The following subsections describe each of
these operations in further detail.
Table 1.
Device Bus Operations
Legend:
L = Logic Low = V
, H = Logic High = V
IH
, V
ID
= 11.5–12.5
V V
HH
= 11.5–12.5
V X = Don’t Care, SA = Sector Address,
A
IN
= Address In, D
IN
= Data In, D
OUT
= Data Out
Notes:
1. Addresses are A21:A0 in word mode.
2. The sector protect and sector unprotect functions may also be implemented via programming equipment. See the “Sector Group
Protection and Unprotection” section.
3. If WP# = V
IL
, the first or last sector remains protected. If WP# = V
IH
, the first or last sector will be protected or unprotected as
determined by the method described in “Sector Group Protection and Unprotection”. All sectors are unprotected when shipped
from the factory (The SecSi Sector may be factory protected depending on version ordered.)
4. D
IN
or D
OUT
as required by command sequence, data polling, or sector protect algorithm (see Figure 2).
VersatileIO
(V
IO
) Control
The VersatileIO (V
IO
) control allows the host system
to set the voltage levels that the device generates and
tolerates on CE# and DQ I/Os to the same voltage
level that is asserted on V
IO
. See
“Ordering Informa-
tion” on page 9
for V
IO
options on this device.
For example, a V
I/O
of 1.65–3.6 volts allows for I/O at
the 1.8 or 3 volt levels, driving and receiving signals to
and from other 1.8 or 3 V devices on the same data
bus.
Requirements for Reading Array Data
To read array data from the outputs, the system must
drive the CE# and OE# pins to V
IL
. CE# is the power
control and selects the device. OE# is the output con-
trol and gates array data to the output pins. WE#
should remain at V
IH
.
The internal state machine is set for reading array data
upon device power-up, or after a hardware reset. This
ensures that no spurious alteration of the memory
content occurs during the power transition. No com-
mand is necessary in this mode to obtain array data.
Operation
CE#
OE#
WE#
RESET#
WP#
ACC
Addresses
(Note 2)
DQ0–
DQ7
DQ8–DQ
15
Read
L
L
H
H
X
X
A
IN
D
OUT
D
OUT
Write (Program/Erase)
L
H
L
H
(Note 3)
X
A
IN
(Note 4)
(Note 4)
Accelerated Program
L
H
L
H
(Note 3)
V
HH
A
IN
(Note 4)
(Note 4)
Standby
V
CC
±
0.3 V
X
X
V
CC
±
0.3 V
X
H
X
High-Z
High-Z
Output Disable
L
H
H
H
X
X
X
High-Z
High-Z
Reset
X
X
X
L
X
X
X
High-Z
High-Z
Sector Group Protect
(Note 2)
L
H
L
V
ID
H
X
SA, A6 =L,
A3=L, A2=L,
A1=H, A0=L
(Note 4)
X
Sector Group Unprotect
(Note 2)
L
H
L
V
ID
H
X
SA, A6=H,
A3=L, A2=L,
A1=H, A0=L
(Note 4)
X
Temporary Sector Group
Unprotect
X
X
X
V
ID
H
X
A
IN
(Note 4)
(Note 4)
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