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參數資料
| 型號： | AM70PDL127BDH66IS |
| 廠商： | SPANSION LLC |
| 元件分類： | 存儲器 |
| 英文描述： | 2 x 64 Megabit (8 M x 16-Bit) CMOS 3.0 Volt-Only Page Mode Flash Memory Data Storage 128 Megabit (8 M x 16-Bit) CMOS |
| 中文描述： | SPECIALTY MEMORY CIRCUIT, PBGA93 |
| 封裝： | 13 X 9 MM, FBGA-93 |
| 文件頁數： | 54/128頁 |
| 文件大?。?/td> | 918K |
| 代理商： | AM70PDL127BDH66IS |
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52
Am70PDL127BDH/Am70PDL129BDH
November 25, 2003
A D V A N C E I N F O R M A T I O N
Command Definitions Tables
Legend:
BA = Address of bank switching to autoselect mode, bypass mode, or
erase operation. Determined by A22:A20, (A21:A20 for PDL129) see
Tables
4
and 5 for more detail.
PA = Program Address (A22:A0) (A21:A0 for PDL129). Addresses
latch on falling edge of WE# or CE#f1/CE#f2 (PDL129 only) pulse,
whichever happens later.
PD = Program Data (DQ15:DQ0) written to location PA. Data latches
on rising edge of WE# or CE#f1/CE#f2 (PDL129 only) pulse,
whichever happens first.
RA = Read Address (A22:A0) (A21:A0 for PDL129).
RD = Read Data (DQ15:DQ0) from location RA.
SA = Sector Address (A22:A12) (A21:A12 for PDL129) for verifying (in
autoselect mode) or erasing.
WD = Write Data. See “Configuration Register” definition for specific
write data. Data latched on rising edge of WE#.
X = Don’t care
Notes:
1.
2.
3.
See
Table 1
for description of bus operations.
All values are in hexadecimal.
Shaded cells in table denote read cycles. All other cycles are
write operations.
During unlock and command cycles, when lower address bits are
555 or 2AAh as shown in table, address bits higher than A11
(except where BA is required) and data bits higher than DQ7 are
don’t cares.
No unlock or command cycles required when bank is reading
array data.
The Reset command is required to return to reading array (or to
erase-suspend-read mode if previously in Erase Suspend) when
bank is in autoselect mode, or if DQ5 goes high (while bank is
providing status information).
Fourth cycle of autoselect command sequence is a read cycle.
System must provide bank address to obtain manufacturer ID or
device ID information. See Autoselect Command Sequence
section for more information.
4.
5.
6.
7.
8.
The data is C0h for factory or customer locked and 80h for factory
locked.
The data is 00h for an unprotected sector group and 01h for a
protected sector group.
10. Device ID must be read across cycles 4, 5, and 6. 20 for
Am29PDL127H and 21 for Am29PDL129H.
11. System may read and program in non-erasing sectors, or enter
autoselect mode, when in Program/Erase Suspend mode.
Program/Erase Suspend command is valid only during a sector
erase operation, and requires bank address.
12. Program/Erase Resume command is valid only during Erase
Suspend mode, and requires bank address.
13. Command is valid when device is ready to read array data or
when device is in autoselect mode.
14. WP#/ACC must be at V
ID
during the entire operation of command.
15. Unlock Bypass Entry command is required prior to any Unlock
Bypass operation.
Unlock Bypass Reset command is required to
return to the reading array.
9.
Table 16.
Memory Array Command Definitions
Command (Notes)
1
1
4
6
Bus Cycles (Notes 1–4)
Addr Data Addr Data
Addr
Data
Addr
Data
Addr
Data
Addr
Data
Read (5)
Reset (6)
RA
XXX
555
555
RD
F0
AA
AA
Autoselect
(Note 7)
Manufacturer ID
Device ID (10)
SecSi Sector Factory
Protect (8)
Sector Group Protect
Verify (9)
2AA
2AA
55
55
555
555
90
90
(BA)X00
(BA)X01
01
7E
(see
note 8)
XX00/
XX01
PD
AA
AA
(BA)X0E (Note 10) (BA)X0F
00
4
555
AA
2AA
55
555
90
X03
4
555
AAA
2AA
55
555
90
(SA)X02
Program
Chip Erase
Sector Erase
Program/Erase Suspend (11)
Program/Erase Resume (12)
CFI Query (13)
Accelerated Program (15)
Unlock Bypass Entry (15)
Unlock Bypass Program (15)
Unlock Bypass Erase (15)
Unlock Bypass CFI (13, 15)
Unlock Bypass Reset (15)
4
6
6
1
1
1
2
3
2
2
1
2
555
555
555
BA
BA
55
XX
555
XX
XX
XX
XXX
AA
AA
AA
B0
30
98
A0
AA
A0
80
98
90
2AA
2AA
2AA
55
55
55
555
555
555
A0
80
80
PA
555
555
2AA
2AA
55
55
555
SA
10
30
PA
2AA
PA
XX
PD
55
PD
10
555
20
XXX
00
相關PDF資料 |
PDF描述 |
|---|---|
| AM70PDL127BDH66IT | 2 x 64 Megabit (8 M x 16-Bit) CMOS 3.0 Volt-Only Page Mode Flash Memory Data Storage 128 Megabit (8 M x 16-Bit) CMOS |
| AM70PDL127BDH85IS | 2 x 64 Megabit (8 M x 16-Bit) CMOS 3.0 Volt-Only Page Mode Flash Memory Data Storage 128 Megabit (8 M x 16-Bit) CMOS |
| AM70PDL129BDH | 2 x 64 Megabit (8 M x 16-Bit) CMOS 3.0 Volt-Only Page Mode Flash Memory Data Storage 128 Megabit (8 M x 16-Bit) CMOS |
| AM70PDL129BDH66IS | 2 x 64 Megabit (8 M x 16-Bit) CMOS 3.0 Volt-Only Page Mode Flash Memory Data Storage 128 Megabit (8 M x 16-Bit) CMOS |
| AM70PDL129BDH66IT | 2 x 64 Megabit (8 M x 16-Bit) CMOS 3.0 Volt-Only Page Mode Flash Memory Data Storage 128 Megabit (8 M x 16-Bit) CMOS |
相關代理商/技術參數 |
參數描述 |
|---|---|
| AM70PDL127BDH66IT | 制造商:SPANSION 制造商全稱:SPANSION 功能描述:2 x 64 Megabit (8 M x 16-Bit) CMOS 3.0 Volt-Only Page Mode Flash Memory Data Storage 128 Megabit (8 M x 16-Bit) CMOS |
| AM70PDL127BDH85I | 制造商:SPANSION 制造商全稱:SPANSION 功能描述:Stacked Multi-Chip Package (MCP/XIP) Flash Memory, Data storage MirrorBit Flash, and pSRAM (XIP) |
| AM70PDL127BDH85IS | 制造商:SPANSION 制造商全稱:SPANSION 功能描述:2 x 64 Megabit (8 M x 16-Bit) CMOS 3.0 Volt-Only Page Mode Flash Memory Data Storage 128 Megabit (8 M x 16-Bit) CMOS |
| AM70PDL127BDH85IT | 制造商:SPANSION 制造商全稱:SPANSION 功能描述:2 x 64 Megabit (8 M x 16-Bit) CMOS 3.0 Volt-Only Page Mode Flash Memory Data Storage 128 Megabit (8 M x 16-Bit) CMOS |
| AM70PDL127CDH | 制造商:SPANSION 制造商全稱:SPANSION 功能描述:Stacked Multi-Chip Package (MCP/XIP) Flash Memory, Data storage MirrorBit Flash, and pSRAM (XIP) |
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