參數資料
型號: AM49DL324BGT85T
廠商: ADVANCED MICRO DEVICES INC
元件分類: 存儲器
英文描述: 32 Megabit (4 M x 8-Bit/2 M x 16-Bit) CMOS 3.0 Volt-only, Simultaneous Operation Flash Memory and 32 Mbit (2M x 16-Bit)
中文描述: SPECIALTY MEMORY CIRCUIT, PBGA73
封裝: 8 X 11.60 MM, PLASTIC, FBGA-73
文件頁數: 55/64頁
文件大小: 571K
代理商: AM49DL324BGT85T
54
Am49DL32xBG
July 19, 2002
P R E L I M I N A R Y
pSRAM AC CHARACTERISTICS
Read Cycle
Notes:
1. t
OD,
t
ODo
, t
BD
, and t
ODW
are defined as the time at which
the outputs achieve the open circuit condition and are
not referenced to output voltage levels.
2. If CE#, LB#, or UB# goes low at the same time or before
WE# goes high, the outputs will remain at high impedance.
3. If CE#, LB#, or UB# goes low at the same time or after WE#
goes low, the outputs will remain at high impedance.
Figure 28.
Psuedo SRAM Read Cycle
Parameter
Symbol
Description
Speed
Unit
70
85
t
RC
t
ACC
t
CO
t
OE
t
BA
t
COE
t
OEE
t
BE
t
OD
t
ODO
t
BD
t
OH
t
PM
t
PC
t
AA
t
AOH
Read Cycle Time
Min
70
85
ns
Address Access Time
Max
70
85
ns
Chip Enable Access Time
Max
70
85
ns
Output Enable Access Time
Max
25
ns
Data Byte Control Access Time
Max
25
ns
Chip Enable Low to Output Active
Min
10
ns
Output Enable Low to Output Active
Min
0
ns
Data Byte Control Low to Output Active
Min
0
ns
Chip Enable High to Output High-Z
Max
20
ns
Output Enable High to Output High-Z
Max
20
ns
Data Byte Control High to Output High-Z
Max
20
ns
Output Data Hold from Address Change
Min
10
ns
Page Mode Time
Min
70
ns
Page Mode Cycle Time
Min
30
ns
Page Mode Address Access Time
Max
30
ns
Page Output Data Hold Time
Min
10
ns
t
RC
t
ACC
Addresses
A0 to A20
CE#1
CE2
OE#
WE#
LB#, UB#
D
OUT
I/O1 to 16
t
CO
t
OH
Fixed High
High-Z
High-Z
t
OE
t
BA
t
OD
t
ODO
t
BD
Valid Data Out
Indeterminate
t
BE
t
OEE
t
COE
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