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參數(shù)資料
| 型號： | AM29PDL128G |
| 廠商： | Spansion Inc. |
| 英文描述： | High Speed CMOS Logic 9-Bit Odd/Even Parity Generator/Checker 14-CDIP -55 to 125 |
| 中文描述： | 128兆位（8米× 16位/ 4米× 32位），3.0伏的CMOS只，同步讀/寫閃存與VersatileIO控制記憶 |
| 文件頁數(shù)： | 32/69頁 |
| 文件大小： | 1181K |
| 代理商： | AM29PDL128G |
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July 29, 2002
Am29PDL128G
31
P R E L I M I N A R Y
Table 11.
System Interface String
Addresses
(Double Word
Mode)
Addresses
(Word Mode)
Data
Description
1Bh
36h
0027h
V
CC
Min. (write/erase)
D7
–
D4: volt, D3
–
D0: 100 millivolt
1Ch
38h
0036h
V
CC
Max. (write/erase)
D7
–
D4: volt, D3
–
D0: 100 millivolt
1Dh
3Ah
0000h
V
PP
Min. voltage (00h = no V
PP
pin present)
1Eh
3Ch
0000h
V
PP
Max. voltage (00h = no V
PP
pin present)
1Fh
3Eh
0004h
Typical timeout per single byte/word write 2
N
μs
20h
40h
0000h
Typical timeout for Min. size buffer write 2
N
μ
s (00h = not supported)
21h
42h
000Ah
Typical timeout per individual block erase 2
N
ms
22h
44h
0000h
Typical timeout for full chip erase 2
N
ms (00h = not supported)
23h
46h
0005h
Max. timeout for byte/word write 2
N
times typical
24h
48h
0000h
Max. timeout for buffer write 2
N
times typical
25h
4Ah
0004h
Max. timeout per individual block erase 2
N
times typical
26h
4Ch
0000h
Max. timeout for full chip erase 2
N
times typical (00h = not supported)
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