- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄375301 > Am29PDL128G70R (Spansion Inc.) 128 Megabit (8 M x 16-Bit/4 M x 32-Bit) CMOS 3.0 Volt-only, Simultaneous Read/ Write Flash Memory with VersatileIO Control PDF資料下載
參數(shù)資料
| 型號： | Am29PDL128G70R |
| 廠商： | Spansion Inc. |
| 英文描述： | 128 Megabit (8 M x 16-Bit/4 M x 32-Bit) CMOS 3.0 Volt-only, Simultaneous Read/ Write Flash Memory with VersatileIO Control |
| 中文描述： | 128兆位（8米× 16位/ 4米× 32位），3.0伏的CMOS只，同步讀/寫閃存與VersatileIO控制記憶 |
| 文件頁數(shù)： | 46/69頁 |
| 文件大小： | 1181K |
| 代理商： | AM29PDL128G70R |
第1頁第2頁第3頁第4頁第5頁第6頁第7頁第8頁第9頁第10頁第11頁第12頁第13頁第14頁第15頁第16頁第17頁第18頁第19頁第20頁第21頁第22頁第23頁第24頁第25頁第26頁第27頁第28頁第29頁第30頁第31頁第32頁第33頁第34頁第35頁第36頁第37頁第38頁第39頁第40頁第41頁第42頁第43頁第44頁第45頁當(dāng)前第46頁第47頁第48頁第49頁第50頁第51頁第52頁第53頁第54頁第55頁第56頁第57頁第58頁第59頁第60頁第61頁第62頁第63頁第64頁第65頁第66頁第67頁第68頁第69頁
July 29, 2002
Am29PDL128G
45
P R E L I M I N A R Y
WRITE OPERATION STATUS
The device provides several bits to determine the status of
a program or erase operation: DQ2, DQ3, DQ5, DQ6, and
DQ7.
Table 18
and the following subsections describe the
function of these bits. DQ7 and DQ6 each offer a method
for determining whether a program or erase operation is
complete or in progress. The device also provides a hard-
ware-based output signal, RY/BY#, to determine whether
an Embedded Program or Erase operation is in progress or
has been completed.
DQ7: Data# Polling
The Data# Polling bit, DQ7, indicates to the host system
whether an Embedded Program or Erase algorithm is in
progress or completed, or whether a bank is in Erase Sus-
pend. Data# Polling is valid after the rising edge of the final
WE# pulse in the command sequence.
During the Embedded Program algorithm, the device out-
puts on DQ7 the complement of the datum programmed to
DQ7. This DQ7 status also applies to programming during
Erase Suspend. When the Embedded Program algorithm is
complete, the device outputs the datum programmed to
DQ7. The system must provide the program address to
read valid status information on DQ7. If a program address
falls within a protected sector, Data# Polling on DQ7 is ac-
tive for approximately 1 μs, then that bank returns to the
read mode.
During the Embedded Erase algorithm, Data# Polling
produces a
“
0
”
on DQ7. When the Embedded Erase
algorithm is complete, or if the bank enters the Erase
Suspend mode, Data# Polling produces a
“
1
”
on DQ7.
The system must provide an address within any of the
sectors selected for erasure to read valid status infor-
mation on DQ7.
After an erase command sequence is written, if all
sectors selected for erasing are protected, Data# Poll-
ing on DQ7 is active for approximately 100 μs, then
the bank returns to the read mode. If not all selected
sectors are protected, the Embedded Erase algorithm
erases the unprotected sectors, and ignores the se-
lected sectors that are protected. However, if the sys-
tem reads DQ7 at an address within a protected
sector, the status may not be valid.
When the system detects DQ7 has changed from the
complement to true data, it can read valid data at
DQ31
–
DQ0 (or DQ15
–
DQ0 for word mode) on the
fol-
lowing
read cycles. Just prior to the completion of an
Embedded Program or Erase operation, DQ7 may
change asynchronously with DQ31
–
DQ16
(DQ15
–
DQ0 for word mode) while Output Enable
(OE#) is asserted low. That is, the device may change
from providing status information to valid data on DQ7.
Depending on when the system samples the DQ7 out-
put, it may read the status or valid data. Even if the de-
vice has completed the program or erase operation
and DQ7 has valid data, the data outputs on
DQ31
–
DQ0 may be still invalid. Valid data on
DQ31
–
DQ0 (or DQ15
–
DQ0 for word mode) will ap-
pear on successive read cycles.
Table 18
shows the outputs for Data# Polling on DQ7.
Figure 5 shows the Data# Polling algorithm. Figure 20
in the
AC Characteristics
section shows the Data#
Polling timing diagram.
Figure 5.
Data# Polling Algorithm
DQ7 = Data
Yes
No
No
DQ5 = 1
No
Yes
Yes
FAIL
PASS
Read DQ7
–
DQ0
Addr = VA
Read DQ7
–
DQ0
Addr = VA
DQ7 = Data
START
Notes:
1. VA = Valid address for programming. During a sector
erase operation, a valid address is any sector address
within the sector being erased. During chip erase, a
valid address is any non-protected sector address.
2. DQ7 should be rechecked even if DQ5 =
“
1
”
because
DQ7 may change simultaneously with DQ5.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| Am29PDL128G80 | 128 Megabit (8 M x 16-Bit/4 M x 32-Bit) CMOS 3.0 Volt-only, Simultaneous Read/ Write Flash Memory with VersatileIO Control |
| Am29PDL128G90 | 128 Megabit (8 M x 16-Bit/4 M x 32-Bit) CMOS 3.0 Volt-only, Simultaneous Read/ Write Flash Memory with VersatileIO Control |
| AM29PDL640G | High Speed CMOS Logic 4-Bit Binary Full Adder with Fast Carry 16-CDIP -55 to 125 |
| AM29PDL310G98WHI | 64 Megabit (4 M x 16-Bit) CMOS 3.0 Volt-only, Simultaneous Read/Write Flash Memory with Enhanced VersatileIO Control |
| AM29PDL310G98WHIN | 64 Megabit (4 M x 16-Bit) CMOS 3.0 Volt-only, Simultaneous Read/Write Flash Memory with Enhanced VersatileIO Control |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| AM29PDL128G70RPEI | 制造商:Spansion 功能描述:FLASH PARALLEL 3V/3.3V 128MBIT 8MX16/4M X 32 70NS 80FBGA - Trays |
| AM29PDL128G80PEF | 制造商:Spansion 功能描述:SPZAM29PDL128G80PEF 128M FLASH EOL100409 |
| AM29PL141BXA | 制造商:AMD 功能描述:* |
| AM29PL141DC | 制造商:Advanced Micro Devices 功能描述:USER PROGRAMMABLE SPECIAL FUNCTION ASIC, 28 Pin, DIP |
| AM29PL160CB-90SF | 制造商:Advanced Micro Devices 功能描述: |
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。