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參數(shù)資料
| 型號： | AM29F040B-55PK |
| 廠商： | Advanced Micro Devices, Inc. |
| 英文描述： | 4 Megabit (512 K x 8-Bit) CMOS 5.0 Volt-only, Uniform Sector Flash Memory |
| 中文描述： | 4兆位（512畝× 8位）的CMOS 5.0伏只，統(tǒng)一部門快閃記憶體 |
| 文件頁數(shù)： | 16/36頁 |
| 文件大?。?/td> | 534K |
| 代理商： | AM29F040B-55PK |
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14
Am29F040B
21445E5
November 1, 2006
D A T A S H E E T
WRITE OPERATION STATUS
The device provides several bits to determine the sta-
tus of a write operation: DQ2, DQ3, DQ5, DQ6, and
DQ7. Table
5
and the following subsections describe
the functions of these bits. DQ7 and DQ6 each offer a
method for determining whether a program or erase
operation is complete or in progress. These three bits
are discussed first.
DQ7: Data# Polling
The Data# Polling bit, DQ7, indicates to the host sys-
tem whether an Embedded Algorithm is in progress or
completed, or whether the device is in Erase Suspend.
Data# Polling is valid after the rising edge of the final
WE# pulse in the program or erase command
sequence.
During the Embedded Program algorithm, the device
outputs on DQ7 the complement of the datum pro-
grammed to DQ7. This DQ7 status also applies to
programming during Erase Suspend. When the Em-
bedded Program algorithm is complete, the device
outputs the datum programmed to DQ7. The system
must provide the program address to read valid status
information on DQ7. If a program address falls within a
protected sector, Data# Polling on DQ7 is active for ap-
proximately 2 μs, then the device returns to reading
array data.
During the Embedded Erase algorithm, Data# Polling
produces a “0” on DQ7. When the Embedded Erase al-
gorithm is complete, or if the device enters the Erase
Suspend mode, Data# Polling produces a “1” on DQ7.
This is analogous to the complement/true datum output
described for the Embedded Program algorithm: the
erase function changes all the bits in a sector to “1”;
prior to this, the device outputs the “complement,” or
“0.” The system must provide an address within any of
the sectors selected for erasure to read valid status in-
formation on DQ7.
After an erase command sequence is written, if all sec-
tors selected for erasing are protected, Data# Polling
on DQ7 is active for approximately 100 μs, then the de-
vice returns to reading array data. If not all selected
sectors are protected, the Embedded Erase algorithm
erases the unprotected sectors, and ignores the se-
lected sectors that are protected.
When the system detects DQ7 has changed from the
complement to true data, it can read valid data at
DQ7–DQ0 on the
following
read cycles. This is be-
cause DQ7 may change asynchronously with
DQ0–DQ6 while Output Enable (OE#) is asserted low.
The Data# Polling Timings (During Embedded Algo-
rithms) figure in the
“AC Characteristics”
section
illustrates this.
Table
5
shows the outputs for Data# Polling on DQ7.
Figure
3
shows the Data# Polling algorithm.
DQ7 = Data
Yes
No
No
DQ5 = 1
No
Yes
Yes
FAIL
PASS
Read DQ7–DQ0
Addr = VA
Read DQ7–DQ0
Addr = VA
DQ7 = Data
START
Notes:
1. VA = Valid address for programming. During a sector
erase operation, a valid address is an address within any
sector selected for erasure. During chip erase, a valid
address is any non-protected sector address.
2. DQ7 should be rechecked even if DQ5 = “1” because
DQ7 may change simultaneously with DQ5.
Figure 3. Data# Polling Algorithm
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相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| AM29F040B-70ED | 制造商:Spansion 功能描述:IC SM FLASH 5V 4MB 制造商:Spansion 功能描述:IC, SM, FLASH, 5V, 4MB |
| AM29F040B-70ED | 制造商:Spansion 功能描述:FLASH MEMORY IC |
| AM29F040B-70ED\T | 制造商:Spansion 功能描述:NOR Flash Parallel 5V 4Mbit 512K x 8bit 70ns 32-Pin TSOP T/R |
| AM29F040B-70EE | 制造商:Spansion 功能描述:NOR Flash Parallel 5V 4Mbit 512K x 8bit 70ns 32-Pin TSOP |
| AM29F040B-70EF | 功能描述:閃存 4M (512Kx8) 70ns 5v Parallel NOR 閃存 RoHS:否 制造商:ON Semiconductor 數(shù)據(jù)總線寬度:1 bit 存儲類型:Flash 存儲容量:2 MB 結(jié)構(gòu):256 K x 8 定時類型: 接口類型:SPI 訪問時間: 電源電壓-最大:3.6 V 電源電壓-最小:2.3 V 最大工作電流:15 mA 工作溫度:- 40 C to + 85 C 安裝風格:SMD/SMT 封裝 / 箱體: 封裝:Reel |
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