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參數(shù)資料
| 型號(hào)： | Am29F002B-55EE |
| 廠商： | Advanced Micro Devices, Inc. |
| 英文描述： | High Speed CMOS Logic Triple 3-Input NOR Gates 14-CDIP -55 to 125 |
| 中文描述： | 2兆位（256畝× 8位）的CMOS 5.0伏，只引導(dǎo)扇區(qū)閃存 |
| 文件頁(yè)數(shù)： | 35/40頁(yè) |
| 文件大小： | 792K |
| 代理商： | AM29F002B-55EE |
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34
Am29F002B/Am29F002NB
November 28, 2000
ERASE AND PROGRAMMING PERFORMANCE
Notes:
1. Typical program and erase times assume the following conditions: 25×C, 5.0 V V
CC
, 1,000,000 cycles. Additionally,
programming typicals assume checkerboard pattern.
2. Under worst case conditions of 90°C, V
CC
= 4.5 V (4.75 V for ±5% devices), 1,000,000 cycles.
3. The typical chip programming time is considerably less than the maximum chip programming time listed, since most bytes
program faster than the maximum program times listed.
4. In the pre-programming step of the Embedded Erase algorithm, all bytes are programmed to 00h before erasure.
5. System-level overhead is the time required to execute the four-bus-cycle sequence for the program command. See Table 5
for further information on command definitions.
6. The device has a minimum guaranteed erase and program cycle endurance of 1,000,000 cycles.
LATCHUP CHARACTERISTICS
Note:
Includes all pins except V
CC
. Test conditions: V
CC
= 5.0 V, one pin at a time. RESET# not available on Am29F002NB.
TSOP PIN CAPACITANCE
Notes:
1. Sampled, not 100% tested.
2. Test conditions T
A
= 25°C, f = 1.0 MHz.
Parameter
Typ (Note 1)
Max (Note 2)
Unit
Comments
Sector Erase Time
1
8
s
Excludes 00h programming
prior to erasure (Note 4)
Chip Erase Time
7
s
Byte Programming Time
7
300
μs
Excludes system level
overhead (Note 5)
Chip Programming Time (Note 3)
1.8
5.4
s
Description
Min
Max
Input voltage with respect to V
SS
on all pins except I/O pins
(including A9, OE#, and RESET#)
–1.0 V
12.5 V
Input voltage with respect to V
SS
on all I/O pins
–1.0 V
V
CC
+ 1.0 V
V
CC
Current
–100 mA
+100 mA
Parameter
Symbol
Parameter Description
Test Setup
Typ
Max
Unit
C
IN
Input Capacitance
V
IN
= 0
6
7.5
pF
C
OUT
Output Capacitance
V
OUT
= 0
8.5
12
pF
C
IN2
Control Pin Capacitance
V
IN
= 0
7.5
9
pF
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PDF描述 |
|---|---|
| AM29F002B-55EI | High Speed CMOS Logic Triple 3-Input NOR Gates 14-CDIP -55 to 125 |
| AM29F002B-55JC | High Speed CMOS Logic Octal D-Type Flip-Flops with Reset 20-CDIP -55 to 125 |
| Am29F002B-55JCB | High Speed CMOS Logic Octal D-Type Flip-Flops with Reset 20-CDIP -55 to 125 |
| Am29F002B-55JE | High Speed CMOS Logic Octal D-Type Flip-Flops with Reset 20-CDIP -55 to 125 |
| AM29F002BB-70 | 2 Megabit (256 K x 8-Bit) CMOS 5.0 Volt-only Boot Sector Flash Memory |
相關(guān)代理商/技術(shù)參數(shù) |
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|---|---|
| AM29F002B-70JC | 制造商:Advanced Micro Devices 功能描述:NOR Flash, 256K x 8, 32 Pin, Plastic, PLCC |
| AM29F002BB-120EC | 制造商:Spansion 功能描述:2M (256KX8) 5V, BOOT BLOCK, BOT, TSOP32, COM - Trays |
| AM29F002BB-120JCT | 制造商:Spansion 功能描述:2M (256KX8) 5V, BOOT BLOCK, BOT, PLCC32, COM, T&R - Tape and Reel |
| AM29F002BB-55EC | 制造商:Spansion 功能描述: |
| AM29F002BB-55JF | 制造商:Spansion 功能描述:NOR Flash Parallel 5V 2Mbit 256K x 8bit 55ns 32-Pin PLCC |
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