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參數(shù)資料
| 型號： | AM29BDS64HE9VMI |
| 廠商： | Spansion Inc. |
| 英文描述： | 128 or 64 Megabit (8 M or 4 M x 16-Bit) CMOS 1.8 Volt-only Simultaneous Read/Write, Burst Mode Flash Memory |
| 中文描述： | 128或64兆位（8米或4個M x 16位）的CMOS 1.8伏，只有同時讀/寫，突發(fā)模式閃存 |
| 文件頁數(shù)： | 61/89頁 |
| 文件大?。?/td> | 913K |
| 代理商： | AM29BDS64HE9VMI |
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May 10, 2006 27024B3
Am29BDS128H/Am29BDS640H
59
D A T A S H E E T
AC CHARACTERISTICS
Notes:
1. Figure shows total number of wait states set to seven cycles. The total number of wait states can be programmed from two
cycles to seven cycles. Clock is set for active rising edge.
2. If any burst address occurs at a 64-word boundary, two additional clock cycle are inserted, and is indicated by RDY.
3. The device is in synchronous mode.
Figure 18.
Synchronous Burst Mode Read
Note:
Figure assumes 7 wait states for initial access and automatic detect synchronous read. D0–D7 in data waveform indicate
the order of data within a given 8-word address range, from lowest to highest. Starting address in figure is the 7th address in
range (A6). See “Requirements for Synchronous (Burst) Read Operation”. The Set Configuration Register command sequence
has been written with A18=1; device will output RDY with valid data.
Figure 19.
8-word Linear Burst with Wrap Around
Da
Da + 1
Da + n
OE#
Data
Addresses
Aa
AVD#
RDY
CLK
CE#
t
CAS
t
AAS
t
AVC
t
AVD
t
AAH
t
OE
t
RACC
t
OEZ
t
CEZ
t
IACC
t
BDH
7 cycles for initial access shown.
Hi-Z
Hi-Z
Hi-Z
1
2
3
4
5
6
7
t
RDYS
t
BACC
t
ACC
t
CR
D6
D7
OE#
Data
Addresses
A6
AVD#
RDY
CLK
CE#
t
CES
t
ACS
t
AVC
t
AVD
t
ACH
t
OE
t
IACC
t
ACC
t
BDH
D0
D1
D5
D6
7 cycles for initial access shown.
Hi-Z
t
RACC
1
2
3
4
5
6
7
t
RDYS
t
BACC
t
CR
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