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參數資料
| 型號： | AM29BDS64HE9VMI |
| 廠商： | Spansion Inc. |
| 英文描述： | 128 or 64 Megabit (8 M or 4 M x 16-Bit) CMOS 1.8 Volt-only Simultaneous Read/Write, Burst Mode Flash Memory |
| 中文描述： | 128或64兆位（8米或4個M x 16位）的CMOS 1.8伏，只有同時讀/寫，突發(fā)模式閃存 |
| 文件頁數： | 36/89頁 |
| 文件大?。?/td> | 913K |
| 代理商： | AM29BDS64HE9VMI |
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34
Am29BDS128H/Am29BDS640H
27024B3 May 10, 2006
D A T A S H E E T
Table 14.
Programmable Wait State Settings
Notes:
1. Upon power-up or hardware reset, the default setting is
seven wait states.
2. RDY will default to being active with data when the Wait
State Setting is set to a total initial access cycle of 2.
It is recommended that the wait state command
sequence be written, even if the default wait state value
is desired, to ensure the device is set as expected. A
hardware reset will set the wait state to the default set-
ting.
Reduced Wait-state Handshaking Option
If the device is equipped with the reduced wait-state
handshaking option, the host system should set
address bits A14–A12 to 010 for the system/device to
execute at maximum speed.
Table 15
describes the typical number of clock cycles
(wait states) for various conditions.
Table 15.
Wait States for Reduced Wait-state
Handshaking
Notes:
1. If the latched address is 3Eh or 3Fh (or an address offset
from either address by a multiple of 64), add two access
cycles to the values listed.
2. In the 8-, 16-, and 32-word burst modes, the address
pointer does not cross 64-word boundaries (3Fh, or
addresses offset from 3Fh by a multiple of 64).
3. Typical initial access cycles may vary depending on
system margin requirements.
A14
A13
A12
Total Initial Access
Cycles
0
0
0
2
0
0
1
3
0
1
0
4
0
1
1
5
1
0
0
6
1
0
1
7 (default)
1
1
0
Reserved
1
1
1
Reserved
System
Frequency
Range
Even Initial
Address
Odd Initial
Address
Device
Speed
Rating
6
–
22 MHz
2
2
D
(54 MHz)
22
–
28 MHz
2
3
28
–
43 MHz
3
4
43
–
54 MHz
4
5
6
–
28 MHz
2
2
E
(66 MHz)
28
–
35 MHz
2
3
35
–
53 MHz
3
4
53
–
66 MHz
4
5
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