參數(shù)資料
型號(hào)： AM29BDS64HE8VMI
廠商： Spansion Inc.
英文描述： 128 or 64 Megabit (8 M or 4 M x 16-Bit) CMOS 1.8 Volt-only Simultaneous Read/Write, Burst Mode Flash Memory
中文描述： 128或64兆位（8米或4個(gè)M x 16位）的CMOS 1.8伏，只有同時(shí)讀/寫，突發(fā)模式閃存
文件頁(yè)數(shù)： 23/89頁(yè)
文件大?。?/td> 913K
代理商： AM29BDS64HE8VMI
May 10, 2006 27024B3
Am29BDS128H/Am29BDS640H
21
D A T A S H E E T
Automatic Sleep Mode
The automatic sleep mode minimizes Flash device
energy consumption. While in asynchronous mode, the
device automatically enables this mode when
addresses remain stable for t
ACC
+ 60 ns. The auto-
matic sleep mode is independent of the CE#, WE#, and
OE# control signals. Standard address access timings
provide new data when addresses are changed. While
in sleep mode, output data is latched and always avail-
able to the system. While in synchronous mode, the
device automatically enables this mode when either the
first active CLK level is greater than t
ACC
or the CLK
runs slower than 5 MHz. Note that a new burst opera-
tion is required to provide new data.
I
CC6
in the
“DC Characteristics” section on page 54
represents the automatic sleep mode current specifica-
tion.
RESET#: Hardware Reset Input
The RESET# input provides a hardware method of
resetting the device to reading array data. When
RESET# is driven low for at least a period of t
RP
, the
device immediately terminates any operation in
progress, tristates all outputs, resets the configuration
register, and ignores all read/write commands for the
duration of the RESET# pulse. The device also resets
the internal state machine to reading array data. The
operation that was interrupted should be reinitiated
once the device is ready to accept another command
sequence, to ensure data integrity.
Current is reduced for the duration of the RESET#
pulse. When RESET# is held at V
SS
± 0.2 V, the device
draws CMOS standby current (I
CC4
). If RESET# is held
at V
IL
but not within V
SS
± 0.2 V, the standby current will
be greater.
RESET# may be tied to the system reset circuitry. A
system reset would thus also reset the Flash memory,
enabling the system to read the boot-up firmware from
the Flash memory.
If RESET# is asserted during a program or erase oper-
ation, the device requires a time of t
READY
(during
Embedded Algorithms) before the device is ready to
read data again. If RESET# is asserted when a
program or erase operation is not executing, the reset
operation is completed within a time of t
READY
(not
during Embedded Algorithms). The system can read
data t
RH
after RESET# returns to V
IH
.
Refer to the
“AC Characteristics” section on page 68
for
RESET# parameters and to
Figure 33, “Reset Tim-
ings,” on page 68
for the timing diagram.
Output Disable Mode
When the OE# input is at V
IH
, output from the device is
disabled. The outputs are placed in the high imped-
ance state.
Figure 1.
Temporary Sector Unprotect Operation
START
Perform Erase or
Program Operations
RESET# = V
IH
Temporary Sector
Unprotect Completed
(Note 2)
RESET# = V
ID
(Note 1)
Notes:
1. All protected sectors unprotected (If WP# = V
IL
,
outermost boot sectors will remain protected).
2. All previously protected sectors are protected once
again.
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