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參數(shù)資料
| 型號： | AM29BDS64HD9VMI |
| 廠商： | Spansion Inc. |
| 英文描述： | 128 or 64 Megabit (8 M or 4 M x 16-Bit) CMOS 1.8 Volt-only Simultaneous Read/Write, Burst Mode Flash Memory |
| 中文描述： | 128或64兆位（8米或4個(gè)M x 16位）的CMOS 1.8伏，只有同時(shí)讀/寫，突發(fā)模式閃存 |
| 文件頁數(shù)： | 42/89頁 |
| 文件大?。?/td> | 913K |
| 代理商： | AM29BDS64HD9VMI |
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Am29BDS128H/Am29BDS640H
27024B3 May 10, 2006
D A T A S H E E T
are ignored. Another Erase Suspend command can be
written after the chip has resumed erasing.
Figure 5.
Erase Operation
Password Program Command
The Password Program Command permits program-
ming the password that is used as part of the hard-
ware protection scheme. The actual password is
64-bits long. 4 Password Program commands are re-
quired to program the password. The user must enter
the unlock cycle, password program command (38h)
and the program address/data for each portion of the
password when programming. There are no provisions
for entering the 2-cycle unlock cycle, the password
program command, and all the password data. There
is no special addressing order required for program-
ming the password. Also, when the password is under-
going programming, Simultaneous Operation is
disabled. Read operations to any memory location will
return the programming status. Once programming is
complete, the user must issue a Read/Reset com-
mand to return the device to normal operation. Once
the Password is written and verified, the Password
Mode Locking Bit must be set in order to prevent verifi-
cation. The Password Program Command is only ca-
pable of programming “0”s. Programming a “1” after a
cell is programmed as a “0” results in a time-out by the
Embedded Program Algorithm with the cell remain-
ing as a “0”. The password is all Fs when shipped from
the factory. All 64-bit password combinations are valid
as a password.
Password Verify Command
The Password Verify Command is used to verify the
Password. The Password is verifiable only when the
Password Mode Locking Bit is not programmed. If the
Password Mode Locking Bit is programmed and the
user attempts to verify the Password, the device will al-
ways drive all Fs onto the DQ data bus.
Also, the device will not operate in Simultaneous Oper-
ation when the Password Verify command is executed.
Only the password is returned regardless of the bank
address. The lower two address bits (A1–A0) are valid
during the Password Verify. Writing the SecSi Sector
Exit command returns the device back to normal oper-
ation.
Password Protection Mode Locking Bit
Program Command
The Password Protection Mode Locking Bit Program
Command programs the Password Protection Mode
Locking Bit, which prevents further verifies or updates
to the password. Once programmed, the Password
Protection Mode Locking Bit cannot be erased and the
Persistent Protection Mode Locking Bit program cir-
cuitry is disabled, thereby forcing the device to remain
in the Password Protection Mode. After issuing
“PL/68h” at the fourth bus cycle, the device requires a
time out period of approximately 150 μs for program-
ming the Password Protection Mode Locking Bit. Then
by writing “PL/48h” at the fifth bus cycle, the device
outputs verify data at DQ0. If DQ0 = 1, then the Pass-
word Protection Mode Locking Bit is programmed. If
not, the system must repeat this program sequence
from the fourth cycle of “PL/68h”. Exiting the Password
Protection Mode Locking Bit Program command is ac-
complished by writing the SecSi Sector Exit command
or Read/Reset command.
Persistent Sector Protection Mode
Locking Bit Program Command
The Persistent Sector Protection Mode Locking Bit
Program Command programs the Persistent Sector
Protection Mode Locking Bit, which prevents the Pass-
word Mode Locking Bit from ever being programmed.
By disabling the program circuitry of the Password
Mode Locking Bit, the device is forced to remain in the
Persistent Sector Protection mode of operation, once
this bit is set. After issuing “SMPL/68h” at the fourth
bus cycle, the device requires a time out period of ap-
proximately 150 μs for programming the Persistent
Protection Mode Locking Bit. Then by writing
“SMPL/48h” at the fifth bus cycle, the device outputs
verify data at DQ0. If DQ0 = 1, then the Persistent Pro-
START
Write Erase
Command Sequence
Data Poll
from System
Data = FFh
No
Yes
Erasure Completed
Embedded
Erase
algorithm
in progress
Notes:
1. See Table 20 for erase command sequence.
2. See the section on DQ3 for information on the sector
erase timer.
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