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參數(shù)資料
| 型號： | AM29BDS643GT7MVAI |
| 廠商： | SPANSION LLC |
| 元件分類： | DRAM |
| 英文描述： | 64 Megabit (4 M x 16-Bit) CMOS 1.8 Volt-only Simultaneous Read/Write, Burst Mode Flash Memory |
| 中文描述： | 4M X 16 FLASH 1.8V PROM, 70 ns, PBGA44 |
| 封裝： | 9.20 X 8 MM, 0.50 MM PITCH, FBGA-44 |
| 文件頁數(shù)： | 35/49頁 |
| 文件大小： | 382K |
| 代理商： | AM29BDS643GT7MVAI |
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May 8, 2006 25692A2
Am29BDS643G
33
D A T A S H E E T
AC CHARACTERISTICS
Synchronous/Burst Read
Notes:
1. Figure shows total number of clock set to five.
2. Figure shows that PS (power saving mode) has been enabled; one additional wait state occurs during initial data Da. Latency
is not present if PS is not enabled.
3. If any burst address occurs at a 64-word boundary, two additional clock cycles are inserted, and is indicated by RDY.
Figure 9.
Burst Mode Read (66 and 54 MHz)
Parameter
Description
7G
(40 MHz)
7M
(54 MHz)
5K
(66 MHz)
Unit
JEDEC
Standard
t
IACC
Initial Access Time
Max
95
87.5
71
ns
t
BACC
Burst Access Time Valid Clock to Output Delay
Max
20
13.5
11
ns
t
AVDS
AVD# Setup Time to CLK
Min
5
4
ns
t
AVDH
AVD# Hold Time from CLK
Min
7
6
ns
t
AVDO
AVD# High to OE# Low
Min
0
0
ns
t
ACS
Address Setup Time to CLK
Min
5
4
ns
t
ACH
Address Hold Time from CLK
Min
7
6
ns
t
BDH
Data Hold Time from Next Clock Cycle
Max
4
4
ns
t
OE
Output Enable to Data, PS, or RDY Valid
Max
20
13.5
11
ns
t
CEZ
Chip Enable to High Z
Max
10
10
ns
t
OEZ
Output Enable to High Z
Max
10
10
ns
t
CES
CE# Setup Time to CLK
Min
5
4
ns
t
RDYS
RDY Setup Time to CLK
Min
5
4
ns
t
RACC
Ready access time from CLK
Max
20
13.5
11
ns
Da
Da + 1
Da + 2
Da + n
OE#
A/DQ0:
A/DQ15
A16:
A21
Aa
AVD#
RDY
CLK
CE#
t
CES
t
ACS
t
AVDS
t
AVDH
t
AVDO
t
ACH
t
BACC
t
RACC
t
OE
t
OEZ
t
CEZ
t
IACC
t
RYDS
t
BDH
Aa
Progra5 cycles for initial access shown.
when PS
enabled
18.5 ns typ. (54 MHz)
Hi-Z
Hi-Z
Hi-Z
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