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參數(shù)資料
| 型號(hào)： | AM29BDS640GTC4WSI |
| 廠商： | SPANSION LLC |
| 元件分類(lèi)： | PROM |
| 英文描述： | 64 Megabit (4 M x 16-Bit) CMOS 1.8 Volt-only Simultaneous Read/Write, Burst Mode Flash Memory |
| 中文描述： | 4M X 16 FLASH 1.8V PROM, 20 ns, PBGA80 |
| 封裝： | 11 X 12 MM, 0.80 MM PITCH, FBGA-80 |
| 文件頁(yè)數(shù)： | 61/77頁(yè) |
| 文件大?。?/td> | 1581K |
| 代理商： | AM29BDS640GTC4WSI |
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62
Am29BDS640G
25903C2 May 9, 2006
Data
Sheet
AC Characteristics
Notes:
1. PA = Program Address, PD = Program Data, VA = Valid Address for reading status bits.
2. “In progress” and “complete” refer to status of program operation.
3. A21–A12 are don’t care during command sequence unlock cycles.
4. Addresses are latched on the first of either the rising edge of AVD# or the active edge of CLK.
5. Either CS# or AVD# is required to go from low to high in between programming command sequences.
6. The Synchronous programming operation is independent of the Set Device Read Mode bit in the Burst Mode
Configuration Register.
7. AVD# must toggle during command sequence unlock cycles.
8. tAH = 45 ns.
9. CLK must not have an active edge while WE# is at VIL.
Figure 24. Alternate Synchronous Program Operation Timings
OE#
CE#
Data
Addresses
AVD
WE#
CLK
VCC
555h
PD
tAH
tWC
tWPH
tWP
PA
tVCS
tDH
tCH
In
Progress
tWHWH1
VA
Complete
VA
Program Command Sequence (last two cycles)
Read Status Data
tDS
tAVDP
A0h
tACS
tCAS
tAVHC
tCSW2
tAS
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