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參數(shù)資料
| 型號(hào)： | AM29BDS640GBD3WSI |
| 廠商： | SPANSION LLC |
| 元件分類(lèi)： | PROM |
| 英文描述： | 64 Megabit (4 M x 16-Bit) CMOS 1.8 Volt-only Simultaneous Read/Write, Burst Mode Flash Memory |
| 中文描述： | 4M X 16 FLASH 1.8V PROM, 14 ns, PBGA80 |
| 封裝： | 11 X 12 MM, 0.80 MM PITCH, FBGA-80 |
| 文件頁(yè)數(shù)： | 73/77頁(yè) |
| 文件大?。?/td> | 1581K |
| 代理商： | AM29BDS640GBD3WSI |
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May 9, 2006 25903C2
Am29BDS640G
73
Data
Sheet
Revision Summary
Revision A (February 13, 2002)
Initial release.
Revision A+1 (February 19, 2002)
Automatic Sleep Mode
Clarified description to indicate that sleep mode is activated when the first CLK
edge occurs after tACC.
Figure 20, Asynchronous Program Operation Timings
Modified to show that CLK is don’t care prior to AVD# going low, and that AVD#
must not be low before CE# transitions low.
Revision A+2 (February 27, 2002)
Extended don’t care section of CLK to falling edge of WE#.
Revision A+3 (May 9, 2002)
Shifted address, clock, and data cycle references in third paragraph up by one.
Corrected data for address 23h.
Added table.
Autoselect Command Sequence
Added bottom boot device IDs to table.
Added bottom boot device IDs to table.
RDY: Ready
Corrected address boundary from 63rd word/3Eh to 64th word/3Fh.
DC Characteristics
Added VIO = VIO min to test conditions for VOL and VOH in table.
Erase/Program Operations table
Added specifications for parameters tCSW1, tCSW2, tCHW, tAHC.
Added note to indicate AVD# must toggle during command sequence unlock cy-
Added figures, which show different timings between addresses, CLK, WE#, and
AVD#.
Added note to indicate AVD# must toggle during data reads.
Shifted address, clock, and data cycle counts up by one.
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