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參數(shù)資料
| 型號： | AM29BDS320GBC8VMI |
| 廠商： | SPANSION LLC |
| 元件分類： | DRAM |
| 英文描述： | 32 Megabit (2 M x 16-Bit), 1.8 Volt-only Simultaneous Read/Write, Burst Mode Flash Memory |
| 中文描述： | 2M X 16 FLASH 1.8V PROM, 90 ns, PBGA64 |
| 封裝： | 8 X 9 MM, 0.80 MM PITCH, FBGA-64 |
| 文件頁數(shù)： | 38/74頁 |
| 文件大?。?/td> | 701K |
| 代理商： | AM29BDS320GBC8VMI |
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36
Am29BDS320G
27243B1 October 1, 2003
P r e l i m i n a r y
Command Definitions
Table 14. Command Definitions
Command Sequence
( Notes)
C
Bus Cycles ( Notes 1– 5)
Third
Addr
Data
First
Second
Addr
Fourth
Fifth
Sixth
Addr
RA
XXX
555
Data
RD
F0
AA
Data
Addr
Data
Addr
Data
Addr
Data
Asynchronous Read (6)
Reset (7)
Manufacturer ID
1
1
4
A
Program
Unlock Bypass
Unlock Bypass Program (12)
Unlock Bypass Sector Erase (12)
Unlock Bypass Chip Erase (12)
Unlock Bypass Reset (13)
Chip Erase
Sector Erase
Erase Suspend (7, 14)
Erase Resume (15)
Sector Lock/Unlock (7)
Set Burst Mode
Configuration Register (16)
CFI Query (17)
2AA
55
(BA)555
90
(BA)X00
0001
Device ID (9)
6
555
AA
2AA
55
(BA)555
90
(BA)X01
227E
(BA)X
0E
(Note
9)
(BA)
X0F
2200
Sector Lock Verify (10)
4
555
AA
2AA
55
(SA)555
90
(SA)X02
0000/0001
Handshaking Option (11)
4
555
AA
2AA
55
(BA)555
90
(BA)X03
0042/0043
4
3
2
2
2
2
6
6
1
1
3
555
555
XXX
XXX
XXX
BA
555
555
BA
BA
BA
AA
AA
A0
80
80
90
AA
AA
B0
30
60
2AA
2AA
PA
SA
XXX
XXX
2AA
2AA
55
55
PD
30
10
00
55
55
555
555
A0
20
PA
PD
555
555
80
80
555
555
AA
AA
2AA
2AA
55
55
555
SA
10
30
BA
60
SLA
60
3
555
AA
2AA
55
(CR)555
C0
1
55
98
Legend:
X = Don’t care
RA = Address of the memory location to be read.
RD = Data read from location RA during read operation.
PA = Address of the memory location to be programmed. Addresses
latch on the rising edge of the AVD# pulse.
PD = Data to be programmed at location PA. Data latches on the
rising edge of WE# pulse.
SA = Address of the sector to be verified (in autoselect mode) or
erased. Address bits A20–A13 uniquely select any sector.
BA = Address of the bank (A20, A19) that is being switched to
Autoselect mode, is in bypass mode, is being erased, or is being
selected for sector lock/unlock.
SLA = Address of the sector to be locked. Set sector address (SA)
and either A6 = 1 for unlocked or A6 = 0 for locked.
CR = Configuration Register address bits A19–A12.
Notes:
1.
2.
3.
See Table
1
for description of bus operations.
All values are in hexadecimal.
Except for the read cycle and the fourth cycle of the autoselect
command sequence, all bus cycles are write cycles.
Data bits DQ15–DQ8 are don’t care in command sequences,
except for RD and PD.
Unless otherwise noted, address bits A20–A12 are don’t cares.
No unlock or command cycles required when bank is reading
array data.
The Reset command is required to return to reading array data
(or to the erase-suspend-read mode if previously in Erase
Suspend) when a bank is in the autoselect mode, or if DQ5 goes
high (while the bank is providing status information) or
performing sector lock/unlock.
The fourth cycle of the autoselect command sequence is a read
cycle. The system must provide the bank address. See the
Autoselect Command Sequence section for more information.
The data in the fifth cycle is 2222 for 1.8 V V
, and 2214 for 3.0
V V
(top boot); 2223 for 1.8 V V
IO
, and 2234 for 3.0 V V
IO
(bottom boot).
4.
5.
6.
7.
8.
9.
10. The data is 0000h for an unlocked sector and 0001h for a locked
sector
11. The data is 0043h for reduced wait-state handshaking and
0042h for standard handshaking.
12. The Unlock Bypass command sequence is required prior to this
command sequence.
13. The Unlock Bypass Reset command is required to return to
reading array data when the bank is in the unlock bypass mode.
14. The system may read and program in non-erasing sectors, or
enter the autoselect mode, when in the Erase Suspend mode.
The Erase Suspend command is valid only during a sector erase
operation, and requires the bank address.
15. The Erase Resume command is valid only during the Erase
Suspend mode, and requires the bank address.
16. See “Set Burst Mode Configuration Register Command
Sequence” for details.
17. Command is valid when device is ready to read array data or
when device is in autoselect mode.
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