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參數(shù)資料
| 型號(hào)： | AM29BDD160GB20CKI |
| 廠商： | Advanced Micro Devices, Inc. |
| 英文描述： | 16 Megabit (1 M x 16-bit/512 K x 32-Bit), CMOS 2.5 Volt-only Burst Mode, Dual Boot, Simultaneous Read/Write Flash Memory |
| 中文描述： | 16兆位（1 M中的x 16-bit/512畝× 32位），2.5伏的CMOS只突發(fā)模式，雙啟動(dòng)，同步讀/寫閃存 |
| 文件頁(yè)數(shù)： | 30/79頁(yè) |
| 文件大?。?/td> | 1368K |
| 代理商： | AM29BDD160GB20CKI |
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28
Am29BDD160G
June 7, 2006
6
.
Exec
u
t
i
ng the Ch
i
p Er
as
e comm
a
nd
is
perm
i
tted
when the
S
ec
Si
s
ector
is
en
ab
led
.
The Ch
i
p Er
as
e
comm
a
nd er
as
e
s
a
ll
s
ector
s
i
n the memory
a
rr
a
y
except for
s
ector 0
i
n top-
b
oot
b
lock conf
i
g
u
r
a
t
i
on
a
nd
s
ector 45
i
n
b
ottom-
b
oot
b
lock conf
i
g
u
r
a
t
i
on
.
The
S
ec
Si
S
ector
is
a
one-t
i
me progr
a
mm
ab
le
memory
a
re
a
th
a
t c
a
nnot
b
e er
as
ed
.
7
.
Exec
u
t
i
ng the
S
ec
Si
S
ector Entry comm
a
nd d
u
r
i
ng
progr
a
m or er
as
e
sus
pend mode
is
a
llowed
.
The
S
ector Er
as
e/Progr
a
m Re
su
me comm
a
nd
is
d
is
-
ab
led wh
i
le the
S
ec
Si
s
ector
is
en
ab
led,
a
nd the
us
er c
a
nnot re
su
me progr
a
mm
i
ng of the memory
a
rr
a
y
u
nt
i
l the Ex
i
t
S
ec
Si
S
ector comm
a
nd
is
wr
i
t-
ten
.
S
ec
Si
S
ector Protect
i
on B
i
t
The
S
ec
Si
S
ector Protect
i
on B
i
t prevent
s
progr
a
m-
m
i
ng of the
S
ec
Si
s
ector memory
a
re
a.
Once
s
et, the
S
ec
Si
s
ector memory
a
re
a
content
s
a
re non-mod
i
f
i
-
ab
le
.
Per
sis
tent Protect
i
on B
i
t Lock
The Per
sis
tent Protect
i
on B
i
t (PPB) Lock
is
a
vol
a
t
i
le
bi
t th
a
t reflect
s
the
s
t
a
te of the P
ass
word Mode Lock-
i
ng B
i
t
a
fter power-
u
p re
s
et
.
If the P
ass
word Mode
Lock
i
ng B
i
t
is
s
et, wh
i
ch
i
nd
i
c
a
te
s
the dev
i
ce
is
i
n
P
ass
word Protect
i
on Mode, the PPB Lock B
i
t
is
a
l
s
o
s
et
a
fter
a
h
a
rdw
a
re re
s
et (RE
S
ET#
ass
erted) or
a
power-
u
p re
s
et
.
The ONLY me
a
n
s
for cle
a
r
i
ng the
PPB Lock B
i
t
i
n P
ass
word Protect
i
on Mode
is
to
issu
e
the P
ass
word Unlock comm
a
nd
.
Su
cce
ss
f
u
l exec
u
t
i
on
of the P
ass
word Unlock comm
a
nd cle
a
r
s
the PPB
Lock B
i
t,
a
llow
i
ng for
s
ector PPB
s
mod
i
f
i
c
a
t
i
on
s.
A
s
-
s
ert
i
ng RE
S
ET#, t
a
k
i
ng the dev
i
ce thro
u
gh
a
power-on
re
s
et, or
issui
ng the PPB Lock B
i
t
S
et comm
a
nd
s
et
s
the PPB Lock B
i
t
ba
ck to
a
“1”
.
If the P
ass
word Mode Lock
i
ng B
i
t
is
not
s
et,
i
nd
i
c
a
t
i
ng
Per
sis
tent
S
ector Protect
i
on Mode, the PPB Lock B
i
t
is
cle
a
red
a
fter power-
u
p or h
a
rdw
a
re re
s
et
.
The PPB
Lock B
i
t
is
s
et
b
y
issui
ng the PPB Lock B
i
t
S
et com-
m
a
nd
.
Once
s
et the only me
a
n
s
for cle
a
r
i
ng the PPB
Lock B
i
t
is
b
y
issui
ng
a
h
a
rdw
a
re or power-
u
p re
s
et
.
The P
ass
word Unlock comm
a
nd
is
i
gnored
i
n Per
sis
-
tent
S
ector Protect
i
on Mode
.
Hardware Data Protect
i
on
The comm
a
nd
s
e
qu
ence re
qui
rement of
u
nlock cycle
s
for progr
a
mm
i
ng or er
asi
ng prov
i
de
s
d
a
t
a
protect
i
on
a
g
ai
n
s
t
i
n
a
dvertent wr
i
te
s.
In
a
dd
i
t
i
on, the follow
i
ng
h
a
rdw
a
re d
a
t
a
protect
i
on me
asu
re
s
prevent
a
cc
i
dent
a
l
er
asu
re or progr
a
mm
i
ng, wh
i
ch m
i
ght otherw
is
e
b
e
c
aus
ed
b
y
s
p
u
r
i
o
us
s
y
s
tem level
si
gn
a
l
s
d
u
r
i
ng V
CC
power-
u
p
a
nd power-down tr
a
n
si
t
i
on
s
, or from
s
y
s
tem
no
is
e
.
Low V
CC
Wr
i
te Inh
i
b
i
t
When V
CC
is
le
ss
th
a
n V
LKO
, the dev
i
ce doe
s
not
a
c-
cept
a
i
te cycle
s.
Th
is
protect
s
d
a
t
a
d
u
r
i
ng V
CC
power-
u
p
a
nd power-down
.
The comm
a
nd reg
is
ter
a
nd
a
ll
i
ntern
a
l er
as
e/progr
a
m c
i
rc
ui
t
s
a
re d
isab
led,
a
nd the dev
i
ce re
s
et
s.
Subs
e
qu
ent wr
i
te
s
a
re
i
gnored
u
nt
i
l V
CC
is
gre
a
ter th
a
n V
LKO
.
The
s
y
s
tem m
us
t pro-
v
i
de the proper
si
gn
a
l
s
to the control p
i
n
s
to prevent
u
n
i
ntent
i
on
a
l wr
i
te
s
when V
CC
is
gre
a
ter th
a
n V
LKO
.
Wr
i
te Pul
s
e “Gl
i
tch” Protect
i
on
No
is
e p
u
l
s
e
s
of le
ss
th
a
n 5 n
s
(typ
i
c
a
l) on OE#, CE#,
or WE# do not
i
n
i
t
ia
te
a
wr
i
te cycle
.
Lo
gi
cal Inh
i
b
i
t
Wr
i
te cycle
s
a
re
i
nh
ibi
ted
b
y hold
i
ng
a
ny one of OE# =
V
IL
, CE# = V
IH
, or WE# = V
IH
.
To
i
n
i
t
ia
te
a
wr
i
te cycle,
CE#
a
nd WE# m
us
t
b
e
a
log
i
c
a
l zero (V
IL
) wh
i
le OE#
is
a
log
i
c
a
l one (V
IH
)
.
Power-Up Wr
i
te Inh
i
b
i
t
If WE# = CE# = V
IL
a
nd OE# = V
IH
d
u
r
i
ng power-
u
p,
the dev
i
ce doe
s
not
a
ccept comm
a
nd
s
on the r
isi
ng
edge of WE#
.
The
i
ntern
a
l
s
t
a
te m
a
ch
i
ne
is
au
tom
a
t
i
-
c
a
lly re
s
et to re
a
d
i
ng
a
rr
a
y d
a
t
a
on power-
u
p
.
V
CC
and V
IO
Power-up And Power-down
S
equenc
i
n
g
The dev
i
ce
i
mpo
s
e
s
no re
s
tr
i
ct
i
on
s
on V
CC
a
nd V
IO
power-
u
p or power-down
s
e
qu
enc
i
ng
.
A
ss
ert
i
ng RE-
S
ET# to V
IL
is
re
qui
red d
u
r
i
ng the ent
i
re V
CC
a
nd V
IO
power
s
e
qu
ence
u
nt
i
l the re
s
pect
i
ve
su
ppl
i
e
s
re
a
ch
the
i
r oper
a
t
i
ng volt
a
ge
s.
Once, V
CC
a
nd V
IO
a
tt
ai
n the
i
r
re
s
pect
i
ve oper
a
t
i
ng volt
a
ge
s
, de-
ass
ert
i
on of RE-
S
ET# to V
IH
is
perm
i
tted
.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| AM29BDD160GB20CKK | 16 Megabit (1 M x 16-bit/512 K x 32-Bit), CMOS 2.5 Volt-only Burst Mode, Dual Boot, Simultaneous Read/Write Flash Memory |
| AM29BDD160GB20CPBE | 16 Megabit (1 M x 16-bit/512 K x 32-Bit), CMOS 2.5 Volt-only Burst Mode, Dual Boot, Simultaneous Read/Write Flash Memory |
| AM29BDD160GB20CPBF | 16 Megabit (1 M x 16-bit/512 K x 32-Bit), CMOS 2.5 Volt-only Burst Mode, Dual Boot, Simultaneous Read/Write Flash Memory |
| AM29BDD160GB20CPBI | 16 Megabit (1 M x 16-bit/512 K x 32-Bit), CMOS 2.5 Volt-only Burst Mode, Dual Boot, Simultaneous Read/Write Flash Memory |
| AM29BDD160GB20CPBK | 16 Megabit (1 M x 16-bit/512 K x 32-Bit), CMOS 2.5 Volt-only Burst Mode, Dual Boot, Simultaneous Read/Write Flash Memory |
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參數(shù)描述 |
|---|---|
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