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參數(shù)資料
| 型號： | AM29BDD160GB20CKI |
| 廠商： | Advanced Micro Devices, Inc. |
| 英文描述： | 16 Megabit (1 M x 16-bit/512 K x 32-Bit), CMOS 2.5 Volt-only Burst Mode, Dual Boot, Simultaneous Read/Write Flash Memory |
| 中文描述： | 16兆位（1 M中的x 16-bit/512畝× 32位），2.5伏的CMOS只突發(fā)模式，雙啟動，同步讀/寫閃存 |
| 文件頁數(shù)： | 15/79頁 |
| 文件大小： | 1368K |
| 代理商： | AM29BDD160GB20CKI |
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June 7, 2006
Am29BDD160G
13
Ver
s
at
i
leI/O (V
IO
) Control
The Ver
sa
t
i
leI/O (V
IO
) control
a
llow
s
the ho
s
t
s
y
s
tem
to
s
et the volt
a
ge level
s
th
a
t the dev
i
ce gener
a
te
s
a
t
i
t
s
d
a
t
a
o
u
tp
u
t
s
a
nd the volt
a
ge
s
toler
a
ted
a
t
i
t
s
d
a
t
a
i
np
u
t
s
to the
sa
me volt
a
ge level th
a
t
is
ass
erted on the
V
IO
p
i
n
.
The o
u
tp
u
t volt
a
ge gener
a
ted on the dev
i
ce
is
deter-
m
i
ned
bas
ed on the V
IO
(V
CCQ
) level
.
A V
IO
of 1
.
65–1
.9
5 volt
s
is
t
a
rgeted to prov
i
de for I/O
toler
a
nce
a
t the 1
.8
volt level
.
A V
CC
a
nd V
IO
of 2
.
5–2
.
75 volt
s
m
a
ke
s
the dev
i
ce
a
p-
pe
a
r
as
2
.
5 volt-only
.
Addre
ss
/Control
si
gn
a
l
s
a
re
3.
6 V toler
a
nt w
i
th the ex-
cept
i
on of CLK
.
Word/Double Word Conf
ig
urat
i
on
The WORD# p
i
n control
s
whether the dev
i
ce d
a
t
a
I/O
p
i
n
s
oper
a
te
i
n the word or do
ub
le word conf
i
g
u
r
a
t
i
on
.
If the WORD# p
i
n
is
s
et
a
t V
IH
, the dev
i
ce
is
i
n do
ub
le
word conf
i
g
u
r
a
t
i
on, DQ
3
1–DQ0
a
re
a
ct
i
ve
a
nd con-
trolled
b
y CE#
a
nd OE#
.
If the WORD# p
i
n
is
s
et
a
t V
IL
, the dev
i
ce
is
i
n word
conf
i
g
u
r
a
t
i
on,
a
nd only d
a
t
a
I/O p
i
n
s
DQ15–DQ0
a
re
a
ct
i
ve
a
nd controlled
b
y CE#
a
nd OE#
.
The d
a
t
a
I/O
p
i
n
s
DQ
3
1–DQ16
a
re tr
i
-
s
t
a
ted
.
Requ
i
rement
s
for Read
i
n
g
Array Data
To re
a
d
a
rr
a
y d
a
t
a
from the o
u
tp
u
t
s
, the
s
y
s
tem m
us
t
dr
i
ve the CE#
a
nd OE# p
i
n
s
to V
IL
.
CE#
is
the power
control
a
nd
s
elect
s
the dev
i
ce
.
OE#
is
the o
u
tp
u
t con-
trol
a
nd g
a
te
s
a
rr
a
y d
a
t
a
to the o
u
tp
u
t p
i
n
s.
WE#
s
ho
u
ld rem
ai
n
a
t V
IH
.
The
i
ntern
a
l
s
t
a
te m
a
ch
i
ne
is
s
et for re
a
d
i
ng
a
rr
a
y d
a
t
a
u
pon dev
i
ce power-
u
p, or
a
fter
a
h
a
rdw
a
re re
s
et
.
Th
is
en
su
re
s
th
a
t no
s
p
u
r
i
o
us
a
lter
a
t
i
on of the memory
content occ
u
r
s
d
u
r
i
ng the power tr
a
n
si
t
i
on
.
No com-
m
a
nd
is
nece
ssa
ry
i
n th
is
mode to o
b
t
ai
n
a
rr
a
y d
a
t
a.
S
t
a
nd
a
rd m
i
croproce
ss
or re
a
d cycle
s
th
a
t
ass
ert v
a
l
i
d
a
ddre
ss
e
s
on the dev
i
ce
a
ddre
ss
i
np
u
t
s
prod
u
ce v
a
l
i
d
d
a
t
a
on the dev
i
ce d
a
t
a
o
u
tp
u
t
s.
The dev
i
ce rem
ai
n
s
en
ab
led for re
a
d
a
cce
ss
u
nt
i
l the comm
a
nd reg
is
ter
content
s
a
re
a
ltered
.
Addre
ss
a
cce
ss
t
i
me (t
ACC
)
is
the del
a
y from
s
t
ab
le
a
d-
dre
ss
e
s
to v
a
l
i
d o
u
tp
u
t d
a
t
a.
The ch
i
p en
ab
le
a
cce
ss
t
i
me (t
CE
)
is
the del
a
y from
s
t
ab
le
a
ddre
ss
e
s
a
nd
s
t
a
-
b
le CE# to v
a
l
i
d d
a
t
a
a
t the o
u
tp
u
t p
i
n
s.
The o
u
tp
u
t en-
ab
le
a
cce
ss
t
i
me (t
OE
)
is
the del
a
y from the f
a
ll
i
ng
edge of OE# to v
a
l
i
d d
a
t
a
a
t the o
u
tp
u
t p
i
n
s
(
assu
m
i
ng
the
a
ddre
ss
e
s
h
a
ve
b
een
s
t
ab
le for
a
t le
as
t t
ACC
–t
OE
t
i
me
a
nd CE# h
as
b
een
ass
erted for
a
t le
as
t t
CE
–t
OE
t
i
me)
.
S
ee “Re
a
d
i
ng Arr
a
y D
a
t
a
” for more
i
nform
a
t
i
on
.
Refer
to the AC Re
a
d Oper
a
t
i
on
s
t
ab
le for t
i
m
i
ng
s
pec
i
f
i
c
a
-
t
i
on
s
a
nd to F
i
g
u
re 15 for the t
i
m
i
ng d
ia
gr
a
m
.
I
CC1
i
n
the DC Ch
a
r
a
cter
is
t
i
c
s
t
ab
le repre
s
ent
s
the
a
ct
i
ve c
u
r-
rent
s
pec
i
f
i
c
a
t
i
on for re
a
d
i
ng
a
rr
a
y d
a
t
a.
Si
multaneou
s
Read/Wr
i
te
Operat
i
on
s
Overv
i
ew and Re
s
tr
i
ct
i
on
s
Overv
i
ew
Si
m
u
lt
a
neo
us
Oper
a
t
i
on
is
a
n
a
dv
a
nce
s
f
u
nct
i
on
a
l
i
ty
prov
i
d
i
ng enh
a
nced
s
peed
a
nd flex
ibi
l
i
ty w
i
th m
i
n
i
m
u
m
overhe
a
d
.
Si
m
u
lt
a
neo
us
Oper
a
t
i
on doe
s
th
is
b
y
a
llow-
i
ng
a
n oper
a
t
i
on to
b
e exec
u
ted (em
b
edded oper
a
t
i
on)
i
n
a
ba
nk (
bus
y
ba
nk), then go
i
ng to the other
ba
nk
(non-
bus
y
ba
nk)
a
nd perform
i
ng de
si
red oper
a
t
i
on
s.
The BDD160’
s
Si
m
u
lt
a
neo
us
Oper
a
t
i
on h
as
b
een opt
i
-
m
i
zed for
a
ppl
i
c
a
t
i
on
s
th
a
t co
u
ld mo
s
t
b
enef
i
t from th
is
c
a
p
abi
l
i
ty
.
The
s
e
a
ppl
i
c
a
t
i
on
s
s
tore code
i
n the
bi
g
ba
nk, wh
i
le
s
tor
i
ng d
a
t
a
i
n the
s
m
a
ll
ba
nk
.
The
b
e
s
t
ex
a
mple of th
is
is
when
a
S
ector Er
as
e Oper
a
t
i
on (
as
a
n em
b
edded oper
a
t
i
on)
i
n the
s
m
a
ll (
bus
y)
ba
nk,
wh
i
le perform
i
ng
a
B
u
r
s
t/
s
ynchrono
us
Re
a
d Oper
a
t
i
on
i
n the
bi
g (non-
bus
y)
ba
nk
.
Re
s
tr
i
ct
i
on
s
The BDD160’
s
Si
m
u
lt
a
neo
us
Oper
a
t
i
on
is
te
s
ted
b
y
exec
u
t
i
ng
a
n em
b
edded oper
a
t
i
on
i
n the
s
m
a
ll (
bus
y)
ba
nk wh
i
le perform
i
ng other oper
a
t
i
on
s
i
n the
bi
g
(non-
bus
y)
ba
nk
.
However, the oppo
si
te c
as
e
is
ne
i
-
ther te
s
ted nor v
a
l
i
d
.
Th
a
t
is
,
i
t
is
not te
s
ted
b
y exec
u
t-
i
ng
a
n em
b
edded oper
a
t
i
on
i
n the
bi
g (
bus
y)
ba
nk
wh
i
le perform
i
ng other oper
a
t
i
on
s
i
n the
s
m
a
ll
(non-
bus
y)
ba
nk
.
S
ee T
ab
le 2 B
a
nk
assi
gnment for
Boot B
a
nk
S
ector Dev
i
ce
s.
Table 2
.
Bank A
ssig
nment for Boot Bank
S
ector Dev
i
ce
s
Al
s
o
s
ee T
ab
le 1
8
, “Allowed Oper
a
t
i
on
s
D
u
r
i
ng
Er
as
e/Progr
a
m
Sus
pend,” on p
a
ge
38.
Al
s
o
s
ee
T
ab
le 12, “
S
ector Addre
ss
e
s
for Top Boot
S
ector De-
v
i
ce
s
,” on p
a
ge 2
9
a
nd
s
ee T
ab
le 1
3
, “
S
ector Ad-
dre
ss
e
s
for Bottom Boot
S
ector Dev
i
ce
s
,” on p
a
ge
3
0
.
Si
multaneou
s
Read/Wr
i
te Operat
i
on
s
W
i
th
Zero Latency
The dev
i
ce
is
c
a
p
ab
le of re
a
d
i
ng d
a
t
a
from one
ba
nk
of memory wh
i
le progr
a
mm
i
ng or er
asi
ng
i
n the other
ba
nk of memory
.
An er
as
e oper
a
t
i
on m
a
y
a
l
s
o
b
e
sus
-
pended to re
a
d from or progr
a
m to
a
nother loc
a
t
i
on
w
i
th
i
n the
sa
me
ba
nk (except the
s
ector
b
e
i
ng
er
as
ed)
.
Refer to the DC Ch
a
r
a
cter
is
t
i
c
s
t
ab
le for
Top Boot
S
ector Dev
i
ce
s
Bottom Boot
S
ector
Dev
i
ce
s
B
a
nk
1
B
a
nk
2
S
m
a
ll B
a
nk
B
i
g B
a
nk
B
i
g B
a
nk
S
m
a
ll B
a
nk
相關PDF資料 |
PDF描述 |
|---|---|
| AM29BDD160GB20CKK | 16 Megabit (1 M x 16-bit/512 K x 32-Bit), CMOS 2.5 Volt-only Burst Mode, Dual Boot, Simultaneous Read/Write Flash Memory |
| AM29BDD160GB20CPBE | 16 Megabit (1 M x 16-bit/512 K x 32-Bit), CMOS 2.5 Volt-only Burst Mode, Dual Boot, Simultaneous Read/Write Flash Memory |
| AM29BDD160GB20CPBF | 16 Megabit (1 M x 16-bit/512 K x 32-Bit), CMOS 2.5 Volt-only Burst Mode, Dual Boot, Simultaneous Read/Write Flash Memory |
| AM29BDD160GB20CPBI | 16 Megabit (1 M x 16-bit/512 K x 32-Bit), CMOS 2.5 Volt-only Burst Mode, Dual Boot, Simultaneous Read/Write Flash Memory |
| AM29BDD160GB20CPBK | 16 Megabit (1 M x 16-bit/512 K x 32-Bit), CMOS 2.5 Volt-only Burst Mode, Dual Boot, Simultaneous Read/Write Flash Memory |
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參數(shù)描述 |
|---|---|
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