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參數(shù)資料
| 型號： | AM29BDD160GB20AKK |
| 廠商： | Advanced Micro Devices, Inc. |
| 英文描述： | 16 Megabit (1 M x 16-bit/512 K x 32-Bit), CMOS 2.5 Volt-only Burst Mode, Dual Boot, Simultaneous Read/Write Flash Memory |
| 中文描述： | 16兆位（1 M中的x 16-bit/512畝× 32位），2.5伏的CMOS只突發(fā)模式，雙啟動，同步讀/寫閃存 |
| 文件頁數(shù)： | 39/79頁 |
| 文件大?。?/td> | 1368K |
| 代理商： | AM29BDD160GB20AKK |
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June 7, 2006
Am29BDD160G
37
Unlock Bypa
ss
Re
s
et Command
The Unlock Byp
ass
Re
s
et comm
a
nd pl
a
ce
s
the dev
i
ce
i
n
s
t
a
nd
a
rd re
a
d/re
s
et oper
a
t
i
ng mode
.
Once exe-
c
u
ted, norm
a
l re
a
d oper
a
t
i
on
s
a
nd
us
er comm
a
nd
s
e-
qu
ence
s
a
re
a
v
ai
l
ab
le for exec
u
t
i
on
.
The Unlock Byp
ass
Progr
a
m Comm
a
nd
is
i
gnored
i
f
the
S
ec
Si
s
ector
is
en
ab
led
.
Ch
i
p Era
s
e Command
The Ch
i
p Er
as
e comm
a
nd
is
us
ed to er
as
e the ent
i
re
fl
as
h memory content
s
of the ch
i
p
b
y
issui
ng
a
si
ngle
comm
a
nd
.
Ch
i
p er
as
e
is
a
si
x-
bus
cycle oper
a
t
i
on
.
There
a
re two “
u
nlock” wr
i
te cycle
s
, followed
b
y wr
i
t
i
ng
the er
as
e “
s
et
u
p” comm
a
nd
.
Two more “
u
nlock” wr
i
te
cycle
s
a
re followed
b
y the ch
i
p er
as
e comm
a
nd
.
Ch
i
p
er
as
e doe
s
not er
as
e protected
s
ector
s.
The ch
i
p er
as
e oper
a
t
i
on
i
n
i
t
ia
te
s
the Em
b
edded
Er
as
e
a
lgor
i
thm, wh
i
ch
au
tom
a
t
i
c
a
lly preprogr
a
m
s
a
nd
ver
i
f
i
e
s
the ent
i
re memory to
a
n
a
ll zero p
a
ttern pr
i
or
to electr
i
c
a
l er
as
e
.
The
s
y
s
tem
is
not re
qui
red to pro-
v
i
de
a
ny control
s
or t
i
m
i
ng
s
d
u
r
i
ng the
s
e oper
a
t
i
on
s.
Note th
a
t
a
hardware re
s
et
i
mmed
ia
tely term
i
n
a
te
s
the progr
a
mm
i
ng oper
a
t
i
on
.
The comm
a
nd
s
e
qu
ence
s
ho
u
ld
b
e re
i
n
i
t
ia
ted once th
a
t
ba
nk h
as
ret
u
rned to
re
a
d
i
ng
a
rr
a
y d
a
t
a
, to en
su
re d
a
t
a
i
ntegr
i
ty
.
The Em
b
edded Er
as
e
a
lgor
i
thm er
as
e
b
eg
i
n
s
on the
r
isi
ng edge of the l
as
t WE# or CE# p
u
l
s
e (wh
i
chever
occ
u
r
s
f
i
r
s
t)
i
n the comm
a
nd
s
e
qu
ence
.
The
s
t
a
t
us
of
the er
as
e oper
a
t
i
on
is
determ
i
ned three w
a
y
s:
■
D
a
t
a
# poll
i
ng of the DQ7 p
i
n (
s
ee
DQ7
:
D
a
t
a
# Poll-
i
ng
)
■
Check
i
ng the
s
t
a
t
us
of the toggle
bi
t DQ6 (
s
ee
DQ6
:
Toggle B
i
t I
)
■
Check
i
ng the
s
t
a
t
us
of the RY/BY# p
i
n (
s
ee
RY/BY#
:
Re
a
dy/B
us
y#
)
Once er
asu
re h
as
b
eg
u
n, only the Er
as
e
Sus
pend
comm
a
nd
is
v
a
l
i
d
.
All other comm
a
nd
s
a
re
i
gnored
.
When the Em
b
edded Er
as
e
a
lgor
i
thm
is
complete, the
dev
i
ce ret
u
rn
s
to re
a
d
i
ng
a
rr
a
y d
a
t
a
,
a
nd
a
ddre
ss
e
s
a
re no longer l
a
tched
.
Note th
a
t
a
n
a
ddre
ss
ch
a
nge
is
re
qui
red to
b
eg
i
n re
a
d v
a
l
i
d
a
rr
a
y d
a
t
a.
F
i
g
u
re 5
i
ll
us
tr
a
te
s
the Em
b
edded Er
as
e Algor
i
thm
.
S
ee the
Er
as
e/Progr
a
m Oper
a
t
i
on
s
t
ab
le
s
i
n
AC Ch
a
r-
a
cter
is
t
i
c
s
for p
a
r
a
meter
s
,
a
nd to F
i
g
u
re 22 for t
i
m
i
ng
d
ia
gr
a
m
s.
S
ector Era
s
e Command
The
S
ector Er
as
e comm
a
nd
is
us
ed to er
as
e
i
nd
i
v
i
d-
ua
l
s
ector
s
or the ent
i
re fl
as
h memory content
s.
S
ec-
tor er
as
e
is
a
si
x-
bus
cycle oper
a
t
i
on
.
There
a
re two
“
u
nlock” wr
i
te cycle
s
, followed
b
y wr
i
t
i
ng the er
as
e “
s
et
u
p” comm
a
nd
.
Two more “
u
nlock” wr
i
te cycle
s
a
re
then followed
b
y the er
as
e comm
a
nd (
3
0h)
.
The
s
ec-
tor
a
ddre
ss
(
a
ny
a
ddre
ss
loc
a
t
i
on w
i
th
i
n the de
si
red
s
ector)
is
l
a
tched on the f
a
ll
i
ng edge of WE# or CE#
(wh
i
chever occ
u
r
s
l
as
t) wh
i
le the comm
a
nd (
3
0h)
is
l
a
tched on the r
isi
ng edge of WE# or CE# (wh
i
chever
occ
u
r
s
f
i
r
s
t)
.
S
pec
i
fy
i
ng m
u
lt
i
ple
s
ector
s
for er
as
e
is
a
ccompl
is
hed
b
y wr
i
t
i
ng the
si
x
bus
cycle oper
a
t
i
on,
as
de
s
cr
ib
ed
ab
ove,
a
nd then follow
i
ng
i
t
b
y
a
dd
i
t
i
on
a
l wr
i
te
s
of only
the l
as
t cycle of the
S
ector Er
as
e comm
a
nd to
a
d-
dre
ss
e
s
or other
s
ector
s
to
b
e er
as
ed
.
The t
i
me
b
e-
tween
S
ector Er
as
e comm
a
nd wr
i
te
s
m
us
t
b
e le
ss
th
a
n
8
0
μs
, otherw
is
e the comm
a
nd
is
re
j
ected
.
It
is
recommended th
a
t proce
ss
or
i
nterr
u
pt
s
b
e d
isab
led
d
u
r
i
ng th
is
t
i
me to g
ua
r
a
ntee th
is
cr
i
t
i
c
a
l t
i
m
i
ng cond
i
-
t
i
on
.
The
i
nterr
u
pt
s
c
a
n
b
e re-en
ab
led
a
fter the l
as
t
S
ector Er
as
e comm
a
nd
is
wr
i
tten
.
A t
i
me-o
u
t of
8
0
μs
from the r
isi
ng edge of the l
as
t WE# (or CE#) w
i
ll
i
n
i
-
t
ia
te the exec
u
t
i
on of the
S
ector Er
as
e comm
a
nd(
s
)
.
If
a
nother f
a
ll
i
ng edge of the WE# (or CE#) occ
u
r
s
w
i
th
i
n
the
8
0
μs
t
i
me-o
u
t w
i
ndow, the t
i
mer
is
re
s
et
.
Once the
8
0
μs
w
i
ndow h
as
t
i
med o
u
t
a
nd er
asu
re h
as
b
eg
u
n,
only the Er
as
e
Sus
pend comm
a
nd
is
recogn
i
zed (
s
ee
S
ector Er
as
e
a
nd Progr
a
m
Sus
pend Comm
a
nd
a
nd
S
ector Er
as
e
a
nd Progr
a
m Re
su
me Comm
a
nd
s
ec-
t
i
on
s
)
.
If th
a
t occ
u
r
s
, the
s
ector er
as
e comm
a
nd
s
e-
qu
ence
s
ho
u
ld
b
e re
i
n
i
t
ia
ted once th
a
t
ba
nk h
as
ret
u
rned to re
a
d
i
ng
a
rr
a
y d
a
t
a
, to en
su
re d
a
t
a
i
ntegr
i
ty
.
Lo
a
d
i
ng the
s
ector er
as
e reg
is
ter
s
m
a
y
b
e done
i
n
a
ny
s
e
qu
ence
a
nd w
i
th
a
ny n
u
m
b
er of
s
ector
s.
S
ector er
as
e doe
s
not re
qui
re the
us
er to progr
a
m the
dev
i
ce pr
i
or to er
as
e
.
The dev
i
ce
au
tom
a
t
i
c
a
lly prepro-
gr
a
m
s
a
ll memory loc
a
t
i
on
s
, w
i
th
i
n
s
ector
s
to
b
e
er
as
ed, pr
i
or to electr
i
c
a
l er
as
e
.
When er
asi
ng
a
s
ec-
tor or
s
ector
s
, the rem
ai
n
i
ng
u
n
s
elected
s
ector
s
or the
wr
i
te protected
s
ector
s
a
re
u
n
a
ffected
.
The
s
y
s
tem
is
not re
qui
red to prov
i
de
a
ny control
s
or t
i
m
i
ng
s
d
u
r
i
ng
s
ector er
as
e oper
a
t
i
on
s.
The Er
as
e
Sus
pend
a
nd
Er
as
e Re
su
me comm
a
nd
s
m
a
y
b
e wr
i
tten
as
often
as
re
qui
red d
u
r
i
ng
a
s
ector er
as
e oper
a
t
i
on
.
A
u
tom
a
t
i
c
s
ector er
as
e oper
a
t
i
on
s
b
eg
i
n on the r
isi
ng
edge of the WE# or CE# p
u
l
s
e of the l
as
t
s
ector er
as
e
comm
a
nd
issu
ed,
a
nd once the
8
0
μs
t
i
me-o
u
t w
i
ndow
h
as
exp
i
red
.
The
s
t
a
t
us
of the
s
ector er
as
e oper
a
t
i
on
is
determ
i
ned three w
a
y
s:
■
D
a
t
a
# poll
i
ng of the DQ7 p
i
n
■
Check
i
ng the
s
t
a
t
us
of the toggle
bi
t DQ6
■
Check
i
ng the
s
t
a
t
us
of the RY/BY# p
i
n
F
u
rther
s
t
a
t
us
of dev
i
ce
a
ct
i
v
i
ty d
u
r
i
ng the
s
ector
er
as
e oper
a
t
i
on
is
determ
i
ned
usi
ng toggle
bi
t DQ2
(refer to
DQ2
:
Toggle B
i
t II
)
.
When the Em
b
edded Er
as
e
a
lgor
i
thm
is
complete, the
dev
i
ce ret
u
rn
s
to re
a
d
i
ng
a
rr
a
y d
a
t
a
,
a
nd
a
ddre
ss
e
s
a
re no longer l
a
tched
.
Note th
a
t
a
n
a
ddre
ss
ch
a
nge
is
re
qui
red to
b
eg
i
n re
a
d v
a
l
i
d
a
rr
a
y d
a
t
a.
相關PDF資料 |
PDF描述 |
|---|---|
| AM29BDD160GB20APBE | 16 Megabit (1 M x 16-bit/512 K x 32-Bit), CMOS 2.5 Volt-only Burst Mode, Dual Boot, Simultaneous Read/Write Flash Memory |
| AM29BDD160GB20APBF | 16 Megabit (1 M x 16-bit/512 K x 32-Bit), CMOS 2.5 Volt-only Burst Mode, Dual Boot, Simultaneous Read/Write Flash Memory |
| AM29BDD160GB20APBI | 16 Megabit (1 M x 16-bit/512 K x 32-Bit), CMOS 2.5 Volt-only Burst Mode, Dual Boot, Simultaneous Read/Write Flash Memory |
| AM29BDD160GB20APBK | 16 Megabit (1 M x 16-bit/512 K x 32-Bit), CMOS 2.5 Volt-only Burst Mode, Dual Boot, Simultaneous Read/Write Flash Memory |
| AM29BDD160GB20CKE | 16 Megabit (1 M x 16-bit/512 K x 32-Bit), CMOS 2.5 Volt-only Burst Mode, Dual Boot, Simultaneous Read/Write Flash Memory |
相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| AM29BDS128HE9VKI | 制造商:Advanced Micro Devices 功能描述:Flash Mem Parallel/Serial 1.8V 128M-Bit 8M x 16 50ns 80-Pin FBGA |
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| AM29C01WW WAF | 制造商:Advanced Micro Devices 功能描述: |
| AM29C10API | 制造商:Rochester Electronics LLC 功能描述:- Bulk |
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