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參數(shù)資料
| 型號(hào)： | AM29BDD160GB20AKK |
| 廠商： | Advanced Micro Devices, Inc. |
| 英文描述： | 16 Megabit (1 M x 16-bit/512 K x 32-Bit), CMOS 2.5 Volt-only Burst Mode, Dual Boot, Simultaneous Read/Write Flash Memory |
| 中文描述： | 16兆位（1 M中的x 16-bit/512畝× 32位），2.5伏的CMOS只突發(fā)模式，雙啟動(dòng)，同步讀/寫閃存 |
| 文件頁(yè)數(shù)： | 20/79頁(yè) |
| 文件大?。?/td> | 1368K |
| 代理商： | AM29BDD160GB20AKK |
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18
Am29BDD160G
June 7, 2006
CE# Control
i
n L
i
near Mode
The CE# (Ch
i
p En
ab
le) p
i
n en
ab
le
s
the Am2
9
BDD160
d
u
r
i
ng re
a
d mode oper
a
t
i
on
s.
CE# m
us
t meet the re-
qui
red
bu
r
s
t re
a
d
s
et
u
p t
i
me
s
for
bu
r
s
t cycle
i
n
i
t
ia
t
i
on
.
If CE#
is
t
a
ken to V
IH
a
t
a
ny t
i
me d
u
r
i
ng the
bu
r
s
t l
i
n-
e
a
r or
bu
r
s
t cycle, the dev
i
ce
i
mmed
ia
tely ex
i
t
s
the
bu
r
s
t
s
e
qu
ence
a
nd flo
a
t
s
the DQ
bus
a
nd IND/WAIT#
si
gn
a
l
.
Re
s
t
a
rt
i
ng
a
bu
r
s
t cycle
is
a
ccompl
is
hed
b
y
t
a
k
i
ng CE#
a
nd ADV# to V
IL
.
ADV# Control In L
i
near Mode
The ADV# (Addre
ss
V
a
l
i
d) p
i
n
is
us
ed to
i
n
i
t
ia
te
a
l
i
n-
e
a
r
bu
r
s
t cycle
a
t the clock edge when CE#
a
nd ADV#
a
re
a
t V
IL
a
nd the dev
i
ce
is
conf
i
g
u
red for e
i
ther l
i
ne
a
r
bu
r
s
t mode oper
a
t
i
on
.
A
bu
r
s
t
a
cce
ss
is
i
n
i
t
ia
ted
a
nd
the
a
ddre
ss
is
l
a
tched on the f
i
r
s
t r
isi
ng CLK edge
when ADV#
is
a
ct
i
ve or
u
pon
a
r
isi
ng ADV# edge,
wh
i
chever occ
u
r
s
f
i
r
s
t
.
If the ADV#
si
gn
a
l
is
t
a
ken to
V
IL
pr
i
or to the end of
a
l
i
ne
a
r
bu
r
s
t
s
e
qu
ence, the pre-
v
i
o
us
a
ddre
ss
is
d
is
c
a
rded
a
nd
subs
e
qu
ent
bu
r
s
t
tr
a
n
s
fer
s
a
re
i
nv
a
l
i
d
u
nt
i
l ADV# tr
a
n
si
t
i
on
s
to V
IH
b
e-
fore
a
clock edge, wh
i
ch
i
n
i
t
ia
te
s
a
new
bu
r
s
t
s
e-
qu
ence
.
RE
S
ET# Control
i
n L
i
near Mode
The RE
S
ET# p
i
n
i
mmed
ia
tely h
a
lt
s
the l
i
ne
a
r
bu
r
s
t
a
c-
ce
ss
when t
a
ken to V
IL
.
The DQ d
a
t
a
bus
a
nd
IND/WAIT#
si
gn
a
l flo
a
t
.
Add
i
t
i
on
a
lly, the Conf
i
g
u
r
a
t
i
on
Reg
is
ter content
s
a
re re
s
et
ba
ck to the def
au
lt cond
i
-
t
i
on where the dev
i
ce
is
pl
a
ced
i
n
as
ynchrono
us
a
c-
ce
ss
mode
.
OE# Control
i
n L
i
near Mode
The OE# (O
u
tp
u
t En
ab
le) p
i
n
is
us
ed to en
ab
le the l
i
n-
e
a
r
bu
r
s
t d
a
t
a
on the DQ d
a
t
a
bus
a
nd the IND/WAIT#
p
i
n
.
De-
ass
ert
i
ng the OE# p
i
n to V
IH
d
u
r
i
ng
a
bu
r
s
t op-
er
a
t
i
on flo
a
t
s
the d
a
t
a
bus
a
nd the IND/WAIT# p
i
n
.
However, the dev
i
ce w
i
ll cont
i
n
u
e to oper
a
te
i
ntern
a
lly
as
i
f the
bu
r
s
t
s
e
qu
ence cont
i
n
u
e
s
u
nt
i
l the l
i
ne
a
r
bu
r
s
t
is
complete
.
The OE# p
i
n doe
s
not h
a
lt the
bu
r
s
t
s
e-
qu
ence, th
is
is
a
ccompl
is
hed
b
y e
i
ther t
a
k
i
ng CE# to
V
IH
or re-
issui
ng
a
new ADV# p
u
l
s
e
.
The DQ
bus
a
nd
IND/WAIT#
si
gn
a
l rem
ai
n
i
n the flo
a
t
s
t
a
te
u
nt
i
l OE#
is
t
a
ken to V
IL
.
IND/WAIT# Operat
i
on
i
n L
i
near Mode
The IND/WAIT#, or End of B
u
r
s
t Ind
i
c
a
tor
si
gn
a
l
(when
i
n l
i
ne
a
r mode
s
),
i
nform
s
the
s
y
s
tem th
a
t the
l
as
t
a
ddre
ss
of
a
bu
r
s
t
s
e
qu
ence
is
on the DQ d
a
t
a
bus.
For ex
a
mple,
i
f
a
4-word l
i
ne
a
r
bu
r
s
t
a
cce
ss
is
Si
xteen L
i
ne
a
r D
a
t
a
Tr
a
n
s
fer
s
(X16 Only)
0-1-2-
3
-4-5-6-7-
8
-
9
-A-B-C-D-E-F (A2
:
A-1/ A
3
-A0 = 0000)
1-2-
3
-4-5-6-7-
8
-
9
-A-B-C-D-E-F-0 (A2
:
A-1/ A
3
-A0 = 0001)
2-
3
-4-5-6-7-
8
-
9
-A-B-C-D-E-F-0-1 (A2
:
A-1/ A
3
-A0 = 0010)
3
-4-5-6-7-
8
-
9
-A-B-C-D-E-F-0-1-2 (A2
:
A-1/ A
3
-A0 = 0011)
4-5-6-7-
8
-
9
-A-B-C-D-E-F-0-1-2-
3
(A
:
A-1/ A
3
-A0 = 0100)
5-6-7-
8
-
9
-A-B-C-D-E-F-0-1-2-
3
-4 (A2
:
A-1/ A
3
-A0 = 0101)
6-7-
8
-
9
-A-B-C-D-E-F-0-1-2-
3
-4-5 (A2
:
A-1/ A
3
-A0 = 0110)
7-
8
-
9
-A-B-C-D-E-F-0-1-2-
3
-4-5-6 (A2
:
A-1/ A
3
-A0 = 0111)
8
-
9
-A-B-C-D-E-F-0-1-2-
3
-4-5-6-7 (A2
:
A-1/ A
3
-A0 = 1000)
9
-A-B-C-D-E-F-0-1-2-
3
-4-5-6-7-
8
(A2
:
A-1/ A
3
-A0 = 1001)
A-B-C-D-E-F-0-1-2-
3
-4-5-6-7-
8
-
9
(A2
:
A-1/ A
3
-A0 = 1010)
B-C-D-E-F-0-1-2-
3
-4-5-6-7-
8
-
9
-A (A2
:
A-1/ A
3
-A0 = 1011)
C-D-E-F-0-1-2-
3
-4-5-6-7-
8
-
9
-A-B (A2
:
A-1/ A
3
-A0 = 1100)
D-E-F-0-1-2-
3
-4-5-6-7-
8
-
9
-A-B-C (A2
:
A-1/ A
3
-A0 = 1101)
E-F-0-1-2-
3
-4-5-6-7-
8
-
9
-A-B-C-D (A2
:
A-1/ A
3
-A0 = 1110)
F-0-1-2-
3
-4-5-6-7-
8
-
9
-A-B-C-D-E (A2
:
A-1/ A
3
-A0 = 1111)
Th
i
rty-Two L
i
ne
a
r D
a
t
a
Tr
a
n
s
fer
s
0-1-2-
3
-4-5-6-7-
8
-
9
-A-B-C-D-E-F-G-H-I-J-K-L-M-N-O-P-Q-R-
S
-T-U-V (A
3:
A-1 = 00000)
1-2-
3
-4-5-6-7-
8
-
9
-A-B-C-D-E-F-G-H-I-J-K-L-M-N-O-P-Q-R-
S
-T-U-V-0 (A
3:
A-1 = 00001)
:
U-V-0-1-2-
3
-4-5-6-7-
8
-
9
-A-B-C-D-E-F-G-H-I-J-K-L-M-N-O-P-Q-R-
S
-T (A
3:
A-1 = 11110)
V-0-1-2-
3
-4-5-6-7-
8
-
9
-A-B-C-D-E-F-G-H-I-J-K-L-M-N-O-P-Q-R-
S
-T-U (A
3:
A-1 = 11111)
Table 6
.
16-B
i
t and
3
2-B
i
t L
i
near and Bur
s
t Data Order (Cont
i
nued)
Data Tran
s
fer
S
equence
(Independent of the WORD#
p
i
n)
Output Data
S
equence (In
i
t
i
al Acce
ss
Addre
ss
)
(x16)
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| AM29BDD160GB20APBE | 16 Megabit (1 M x 16-bit/512 K x 32-Bit), CMOS 2.5 Volt-only Burst Mode, Dual Boot, Simultaneous Read/Write Flash Memory |
| AM29BDD160GB20APBF | 16 Megabit (1 M x 16-bit/512 K x 32-Bit), CMOS 2.5 Volt-only Burst Mode, Dual Boot, Simultaneous Read/Write Flash Memory |
| AM29BDD160GB20APBI | 16 Megabit (1 M x 16-bit/512 K x 32-Bit), CMOS 2.5 Volt-only Burst Mode, Dual Boot, Simultaneous Read/Write Flash Memory |
| AM29BDD160GB20APBK | 16 Megabit (1 M x 16-bit/512 K x 32-Bit), CMOS 2.5 Volt-only Burst Mode, Dual Boot, Simultaneous Read/Write Flash Memory |
| AM29BDD160GB20CKE | 16 Megabit (1 M x 16-bit/512 K x 32-Bit), CMOS 2.5 Volt-only Burst Mode, Dual Boot, Simultaneous Read/Write Flash Memory |
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