參數(shù)資料
型號(hào)： AM29BDD160GB17CPBK
廠商： Advanced Micro Devices, Inc.
英文描述： 16 Megabit (1 M x 16-bit/512 K x 32-Bit), CMOS 2.5 Volt-only Burst Mode, Dual Boot, Simultaneous Read/Write Flash Memory
中文描述： 16兆位（1 M中的x 16-bit/512畝× 32位），2.5伏的CMOS只突發(fā)模式，雙啟動(dòng)，同步讀/寫閃存
文件頁數(shù)： 36/79頁
文件大小： 1368K
代理商： AM29BDD160GB17CPBK
34
Am29BDD160G
June 7, 2006
COMMAND DEFINITION
S
Wr
i
t
i
ng
s
pec
i
f
i
c
a
ddre
ss
a
nd d
a
t
a
comm
a
nd
s
or
s
e-
qu
ence
s
i
nto the comm
a
nd reg
is
ter
i
n
i
t
ia
te
s
dev
i
ce op-
er
a
t
i
on
s.
T
ab
le
s
1
8
-21
def
i
ne the v
a
l
i
d reg
is
ter
comm
a
nd
s
e
qu
ence
s.
Wr
i
t
i
ng
i
ncorrect addre
ss
and
data value
s
or wr
i
t
i
ng them
i
n the
i
mproper
s
e-
quence
re
s
et
s
the dev
i
ce to re
a
d
i
ng
a
rr
a
y d
a
t
a.
All
a
ddre
ss
e
s
a
re l
a
tched on the f
a
ll
i
ng edge of WE#
or CE#, wh
i
chever h
a
ppen
s
l
a
ter
.
All d
a
t
a
is
l
a
tched on
the r
isi
ng edge of WE# or CE#, wh
i
chever h
a
ppen
s
f
i
r
s
t
.
Refer to the
AC Ch
a
r
a
cter
is
t
i
c
s
s
ect
i
on for t
i
m
i
ng
d
ia
gr
a
m
s.
Read
i
n
g
Array Data
i
n Non-bur
s
t Mode
The dev
i
ce
is
au
tom
a
t
i
c
a
lly
s
et to re
a
d
i
ng
a
rr
a
y d
a
t
a
a
fter dev
i
ce power-
u
p
.
No comm
a
nd
s
a
re re
qui
red to
retr
i
eve d
a
t
a.
The dev
i
ce
is
a
l
s
o re
a
dy to re
a
d
a
rr
a
y
d
a
t
a
a
fter complet
i
ng
a
n Em
b
edded Progr
a
m or Em-
b
edded Er
as
e
a
lgor
i
thm
.
After the dev
i
ce
a
ccept
s
a
n Er
as
e
Sus
pend com-
m
a
nd, the dev
i
ce enter
s
the Er
as
e
Sus
pend mode
.
The
s
y
s
tem c
a
n re
a
d
a
rr
a
y d
a
t
a
usi
ng the
s
t
a
nd
a
rd
re
a
d t
i
m
i
ng
s
, except th
a
t
i
f
i
t re
a
d
s
a
t
a
n
a
ddre
ss
w
i
th
i
n er
as
e-
sus
pended
s
ector
s
, the dev
i
ce o
u
tp
u
t
s
s
t
a
t
us
d
a
t
a.
After complet
i
ng
a
progr
a
mm
i
ng oper
a
-
t
i
on
i
n the Er
as
e
Sus
pend mode, the
s
y
s
tem m
a
y
once
a
g
ai
n re
a
d
a
rr
a
y d
a
t
a
w
i
th the
sa
me except
i
on
.
S
ee
S
ector Er
as
e
a
nd Progr
a
m
Sus
pend Comm
a
nd
for more
i
nform
a
t
i
on on th
is
mode
.
The
s
y
s
tem
m
us
t
issu
e the re
s
et comm
a
nd to re-en-
ab
le the dev
i
ce for re
a
d
i
ng
a
rr
a
y d
a
t
a
i
f DQ5 goe
s
h
i
gh,
or wh
i
le
i
n the
au
to
s
elect mode
.
S
ee the
The progr
a
m-
m
i
ng of the PPB Lock B
i
t for
a
g
i
ven
s
ector c
a
n
b
e ver-
i
f
i
ed
b
y wr
i
t
i
ng
a
PPB Lock B
i
t
s
t
a
t
us
ver
i
fy comm
a
nd
to the dev
i
ce
.
s
ect
i
on
.
S
ee
a
l
s
o
A
s
ynchrono
us
Re
a
d Oper
a
t
i
on (Non-B
u
r
s
t)
i
n
the
Key to
S
w
i
tch
i
ng W
a
veform
s
s
ect
i
on for more
i
nform
a
t
i
on
.
S
ee the
S
ector Er
as
e
a
nd Progr
a
m Re
su
me
Comm
a
nd
s
ect
i
on
s
for more
i
nform
a
t
i
on on th
is
mode
.
Read
i
n
g
Array Data
i
n Bur
s
t Mode
The dev
i
ce
is
c
a
p
ab
le of very f
as
t B
u
r
s
t mode re
a
d op-
er
a
t
i
on
s.
The conf
i
g
u
r
a
t
i
on reg
is
ter
s
et
s
the re
a
d con-
f
i
g
u
r
a
t
i
on,
bu
r
s
t order, fre
qu
ency conf
i
g
u
r
a
t
i
on,
a
nd
bu
r
s
t length
.
Upon power on, the dev
i
ce def
au
lt
s
to the
as
ynchro-
no
us
mode
.
In th
is
mode, CLK,
a
nd ADV#
a
re
i
gnored
.
The dev
i
ce oper
a
te
s
l
i
ke
a
convent
i
on
a
l Fl
as
h dev
i
ce
.
D
a
t
a
is
a
v
ai
l
ab
le t
ACC
/t
CE
n
a
no
s
econd
s
a
fter
a
ddre
ss
b
ecome
s
s
t
ab
le, CE#
b
ecome
ass
erted
.
The dev
i
ce
enter
s
the
bu
r
s
t mode
b
y en
ab
l
i
ng
s
ynchrono
us
bu
r
s
t
re
a
d
s
i
n the conf
i
g
u
r
a
t
i
on reg
is
ter
.
The dev
i
ce ex
i
t
s
bu
r
s
t mode
b
y d
isab
l
i
ng
s
ynchrono
us
bu
r
s
t re
a
d
s
i
n
the conf
i
g
u
r
a
t
i
on reg
is
ter
.
(
S
ee
Comm
a
nd Def
i
n
i
t
i
on
s
)
.
The RE
S
ET# comm
a
nd w
i
ll not term
i
n
a
te the B
u
r
s
t
mode
.
S
y
s
tem re
s
et (power on re
s
et) w
i
ll term
i
n
a
te
the B
u
r
s
t mode
.
The dev
i
ce h
as
the reg
u
l
a
r control p
i
n
s
,
i.
e
.
Ch
i
p En-
ab
le (CE#), Wr
i
te En
ab
le (WE#),
a
nd O
u
tp
u
t En
ab
le
(OE#) to control norm
a
l re
a
d
a
nd wr
i
te oper
a
t
i
on
s.
Moreover, three
a
dd
i
t
i
on
a
l control p
i
n
s
h
a
ve
b
een
a
dded to
a
llow e
as
y
i
nterf
a
ce w
i
th m
i
n
i
m
a
l gl
u
e log
i
c
to
a
w
i
de r
a
nge of m
i
croproce
ss
or
s
/ m
i
crocontroller
s
for h
i
gh perform
a
nce B
u
r
s
t re
a
d c
a
p
abi
l
i
ty
.
The
s
e
a
d-
d
i
t
i
on
a
l p
i
n
s
a
re Addre
ss
V
a
l
i
d (ADV#)
a
nd Clock
(CLK)
.
CE#, OE#,
a
nd WE#
a
re
as
ynchrono
us
(rel
a
-
t
i
ve to CLK)
.
The B
u
r
s
t mode re
a
d oper
a
t
i
on
is
a
s
yn-
chrono
us
oper
a
t
i
on t
i
ed to the edge of the clock
.
The
m
i
croproce
ss
or / m
i
crocontroller
su
ppl
i
e
s
only the
i
n
i
-
t
ia
l
a
ddre
ss
,
a
ll
subs
e
qu
ent
a
ddre
ss
e
s
a
re
au
tom
a
t
i
-
c
a
lly gener
a
ted
b
y the dev
i
ce w
i
th
a
t
i
m
i
ng def
i
ned
b
y
the Conf
i
g
u
r
a
t
i
on Reg
is
ter def
i
n
i
t
i
on
.
The B
u
r
s
t re
a
d
cycle con
sis
t
s
of
a
n
a
ddre
ss
ph
as
e
a
nd
a
corre
s
pond-
i
ng d
a
t
a
ph
as
e
.
D
u
r
i
ng the
a
ddre
ss
ph
as
e, the Addre
ss
V
a
l
i
d (ADV#)
p
i
n
is
ass
erted (t
a
ken Low) for one clock per
i
od
.
To-
gether w
i
th the edge of the CLK, the
s
t
a
rt
i
ng
bu
r
s
t
a
d-
dre
ss
is
lo
a
ded
i
nto the
i
ntern
a
l B
u
r
s
t Addre
ss
Co
u
nter
.
The
i
ntern
a
l B
u
r
s
t Addre
ss
Co
u
nter c
a
n
b
e
conf
i
g
u
red to e
i
ther the L
i
ne
a
r mode
s
(
S
ee “In
i
t
ia
l Ac-
ce
ss
Del
a
y Conf
i
g
u
r
a
t
i
on”)
.
D
u
r
i
ng the d
a
t
a
ph
as
e, the f
i
r
s
t
bu
r
s
t d
a
t
a
is
a
v
ai
l
ab
le
a
fter the
i
n
i
t
ia
l
a
cce
ss
t
i
me del
a
y def
i
ned
i
n the Conf
i
g-
u
r
a
t
i
on Reg
is
ter
.
For
subs
e
qu
ent
bu
r
s
t d
a
t
a
, every r
is
-
i
ng (or f
a
ll
i
ng) edge of the CLK w
i
ll tr
i
gger the o
u
tp
u
t
d
a
t
a
w
i
th the
bu
r
s
t o
u
tp
u
t del
a
y
a
nd
s
e
qu
ence def
i
ned
i
n the Conf
i
g
u
r
a
t
i
on Reg
is
ter
.
T
ab
le
s
17–20
s
how
a
ll the comm
a
nd
s
exec
u
ted
b
y the
dev
i
ce
.
The dev
i
ce
au
tom
a
t
i
c
a
lly power
s
u
p
i
n the
re
a
d/re
s
et
s
t
a
te
.
It
is
not nece
ssa
ry to
issu
e
a
re
a
d/re-
s
et comm
a
nd
a
fter power-
u
p or h
a
rdw
a
re re
s
et
.
Read/Re
s
et Command
After power-
u
p or h
a
rdw
a
re re
s
et, the Am2
9
BDD160
au
tom
a
t
i
c
a
lly enter the re
a
d
s
t
a
te
.
It
is
not nece
ssa
ry
to
issu
e the re
s
et comm
a
nd
a
fter power-
u
p or h
a
rd-
w
a
re re
s
et
.
S
t
a
nd
a
rd m
i
croproce
ss
or cycle
s
retr
i
eve
a
rr
a
y d
a
t
a
, however,
a
fter power-
u
p, only
as
ynchro-
no
us
a
cce
ss
e
s
a
re perm
i
tted
si
nce the Conf
i
g
u
r
a
t
i
on
Reg
is
ter
is
a
t
i
t
s
re
s
et
s
t
a
te w
i
th
bu
r
s
t
a
cce
ss
e
s
d
is
-
ab
led
.
The Re
s
et comm
a
nd
is
exec
u
ted when the
us
er need
s
to ex
i
t
a
ny of the other
us
er comm
a
nd
s
e
qu
ence
s
(
su
ch
as
au
to
s
elect, progr
a
m, ch
i
p er
as
e, etc
.
) to re-
t
u
rn to re
a
d
i
ng
a
rr
a
y d
a
t
a.
There
is
no l
a
tency
b
e-
tween exec
u
t
i
ng the Re
s
et comm
a
nd
a
nd re
a
d
i
ng
a
rr
a
y d
a
t
a.
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