參數(shù)資料
型號(hào)： AM29BDD160GB17CPBI
廠商： Advanced Micro Devices, Inc.
英文描述： 16 Megabit (1 M x 16-bit/512 K x 32-Bit), CMOS 2.5 Volt-only Burst Mode, Dual Boot, Simultaneous Read/Write Flash Memory
中文描述： 16兆位（1 M中的x 16-bit/512畝× 32位），2.5伏的CMOS只突發(fā)模式，雙啟動(dòng)，同步讀/寫閃存
文件頁數(shù)： 48/79頁
文件大小： 1368K
代理商： AM29BDD160GB17CPBI
46
Am29BDD160G
June 7, 2006
DYB = Dyn
a
m
i
c Protect
i
on B
i
t
OW = Addre
ss
(A5–A0)
is
(011X10)
.
PPB = Per
sis
tent Protect
i
on B
i
t
PWA = P
ass
word Addre
ss.
A0
s
elect
s
b
etween the low
a
nd h
i
gh
32-
bi
t port
i
on
s
of the 64-
bi
t P
ass
word
PWD = P
ass
word D
a
t
a.
M
us
t
b
e wr
i
tten over two cycle
s.
PL = P
ass
word Protect
i
on Mode Lock Addre
ss
(A5–A0)
is
(001X10)
RD(0) = Re
a
d D
a
t
a
DQ0 protect
i
on
i
nd
i
c
a
tor
bi
t
.
If protected, DQ0= 1,
i
f
u
nprotected, DQ0 = 0
.
RD(1) = Re
a
d D
a
t
a
DQ1 protect
i
on
i
nd
i
c
a
tor
bi
t
.
If protected, DQ1 =
1,
i
f
u
nprotected, DQ1 = 0
.
SA = Sector Addre
ss
where
s
ec
u
r
i
ty comm
a
nd
a
ppl
i
e
s.
Addre
ss
bi
t
s
A18
:
A11
u
n
iqu
ely
s
elect
a
ny
s
ector
.
SL = Per
sis
tent Protect
i
on Mode Lock Addre
ss
(A5–A0)
is
(010X10)
WP = PPB Addre
ss
(A5–A0)
is
(111X10)
X = Don’t c
a
re
PPMLB = P
ass
word Protect
i
on Mode Lock
i
ng B
i
t
SPMLB = Per
sis
tent Protect
i
on Mode Lock
i
ng B
i
t
1
.
2
.
3
.
See T
ab
le 1 for de
s
cr
i
pt
i
on of
bus
oper
a
t
i
on
s.
All v
a
l
u
e
s
a
re
i
n hex
a
dec
i
m
a
l
.
Sh
a
ded cell
s
i
n t
ab
le denote re
a
d cycle
s.
All other cycle
s
a
re
wr
i
te oper
a
t
i
on
s.
D
u
r
i
ng
u
nlock cycle
s
, (lower
a
ddre
ss
bi
t
s
a
re 555 or 2AAh
as
s
hown
i
n t
ab
le)
a
ddre
ss
bi
t
s
h
i
gher th
a
n A11 (except where BA
is
re
qui
red)
a
nd d
a
t
a
bi
t
s
h
i
gher th
a
n DQ7
a
re don’t c
a
re
s.
The re
s
et comm
a
nd ret
u
rn
s
the dev
i
ce to re
a
d
i
ng the
a
rr
a
y
.
The fo
u
rth cycle progr
a
m
s
the
a
ddre
ss
ed lock
i
ng
bi
t
.
The f
i
fth
a
nd
si
xth cycle
s
a
re
us
ed to v
a
l
i
d
a
te whether the
bi
t h
as
b
een f
u
lly
progr
a
mmed
.
If DQ0 (
i
n the
si
xth cycle) re
a
d
s
0, the progr
a
m
comm
a
nd m
us
t
b
e
issu
ed
a
nd ver
i
f
i
ed
a
g
ai
n
.
4
.
5
.
6
.
7
.
8
.
D
a
t
a
is
l
a
tched on the r
isi
ng edge of WE#
.
The ent
i
re fo
u
r
bus
-cycle
s
e
qu
ence m
us
t
b
e entered for e
a
ch
port
i
on of the p
ass
word
.
The fo
u
rth cycle er
as
e
s
a
ll PPB
s.
The f
i
fth
a
nd
si
xth cycle
s
a
re
us
ed to v
a
l
i
d
a
te whether the
bi
t
s
h
a
ve
b
een f
u
lly er
as
ed
.
If DQ0
(
i
n the
si
xth cycle) re
a
d
s
1, the er
as
e comm
a
nd m
us
t
b
e
issu
ed
a
nd ver
i
f
i
ed
a
g
ai
n
.
10
.
Before
issui
ng the er
as
e comm
a
nd,
a
ll PPB
s
s
ho
u
ld
b
e
progr
a
mmed
i
n order to prevent over-er
asu
re of PPB
s.
11
.
In the fo
u
rth cycle, 00h
i
nd
i
c
a
te
s
PPB
s
et; 01h
i
nd
i
c
a
te
s
PPB not
s
et
.
12
.
The
s
t
a
t
us
of
a
dd
i
t
i
on
a
l PPB
s
a
nd DYB
s
m
a
y
b
e re
a
d (follow
i
ng
the fo
u
rth cycle) w
i
tho
u
t re
issui
ng the ent
i
re comm
a
nd
s
e
qu
ence
.
9
.
Table 20
.
S
ector Protect
i
on Command Def
i
n
i
t
i
on
s
(x
3
2 Mode)
Command (Note
s
)
C
s
Bu
s
Cycle
s
(Note
s
1-4)
Th
i
rd
Addr
Data
F
i
r
s
t
S
econd
Fourth
F
i
fth
Si
xth
Addr Data Addr Data
XXX
F0
555
AA
555
AA
555
AA
555
AA
555
AA
555
AA
555
AA
555
AA
555
AA
555
AA
555
AA
555
AA
555
AA
555
AA
555
AA
555
AA
555
AA
555
AA
555
AA
Addr
Data
Addr
Data
Addr
Data
Re
s
et
S
ec
Si
S
ector Entry
S
ec
Si
S
ector Ex
i
t
S
ec
Si
Protect
i
on B
i
t Progr
a
m (5, 6)
S
ec
Si
Protect
i
on B
i
t
S
t
a
t
us
P
ass
word Progr
a
m (5, 7,
8
)
P
ass
word Ver
i
fy
P
ass
word Unlock (7,
8
)
PPB Progr
a
m (5, 6)
All PPB Er
as
e (5,
9
, 10)
PPB
S
t
a
t
us
(11, 12)
PPB Lock B
i
t
S
et
PPB Lock B
i
t
S
t
a
t
us
DYB Wr
i
te (7)
DYB Er
as
e (7)
DYB
S
t
a
t
us
(12)
PPMLB Progr
a
m (5,6)
PPMLB
S
t
a
t
us
(5)
S
PMLB Progr
a
m (5, 6)
S
PMLB
S
t
a
t
us
(5)
1
3
4
6
6
4
4
5
6
6
4
3
4
4
4
4
6
6
6
6
2AA
2AA
2AA
2AA
2AA
2AA
2AA
2AA
2AA
2AA
2AA
2AA
2AA
2AA
2AA
2AA
2AA
2AA
2AA
55
55
55
55
55
55
55
55
55
55
55
55
55
55
55
55
55
55
55
555
555
555
555
555
555
555
555
555
555
555
88
9
0
60
60
38
C
8
2
8
60
60
9
0
7
8
5
8
4
8
4
8
5
8
60
60
60
60
XX
OW
OW
00
6
8
OW
4
8
OW
RD(0)
RD(0)
PWA[0-1] PWD[0-1]
PWA[0-1] PWD[0-1]
PWA[0-1] PWD[0-1]
(
S
A)WP
WP
(
S
A)X02
6
8
60
(
S
A)WP
(
S
A)WP
4
8
40
(
S
A)WP RD(0)
(
S
A)WP RD(0)
00/01
(BA) 555
555
555
(BA) 555
555
555
555
555
S
A
S
A
S
A
S
A
PL
PL
S
L
S
L
RD(1)
X1
X0
RD(0)
6
8
RD(0)
6
8
RD(0)
PL
4
8
PL
RD(0)
S
L
4
8
S
L
RD(0)
相關(guān)PDF資料
PDF描述
AM29BDD160GB17CPBK 16 Megabit (1 M x 16-bit/512 K x 32-Bit), CMOS 2.5 Volt-only Burst Mode, Dual Boot, Simultaneous Read/Write Flash Memory
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