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| 型號(hào)： | AM29BDD160GB17CKK |
| 廠商： | Advanced Micro Devices, Inc. |
| 英文描述： | 16 Megabit (1 M x 16-bit/512 K x 32-Bit), CMOS 2.5 Volt-only Burst Mode, Dual Boot, Simultaneous Read/Write Flash Memory |
| 中文描述： | 16兆位（1 M中的x 16-bit/512畝× 32位），2.5伏的CMOS只突發(fā)模式，雙啟動(dòng)，同步讀/寫(xiě)閃存 |
| 文件頁(yè)數(shù)： | 51/79頁(yè) |
| 文件大?。?/td> | 1368K |
| 代理商： | AM29BDD160GB17CKK |
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June 7, 2006
Am29BDD160G
49
WRITE OPERATION
S
TATU
S
The dev
i
ce prov
i
de
s
s
ever
a
l
bi
t
s
to determ
i
ne the
s
t
a
-
t
us
of
a
wr
i
te oper
a
t
i
on
:
DQ2, DQ
3
, DQ5, DQ6, DQ7,
a
nd RY/BY#
.
T
ab
le 2
3
a
nd the follow
i
ng
subs
ect
i
on
s
de
s
cr
ib
e the f
u
nct
i
on
s
of the
s
e
bi
t
s.
DQ7, RY/BY#,
a
nd
DQ6 e
a
ch offer
a
method for determ
i
n
i
ng whether
a
progr
a
m or er
as
e oper
a
t
i
on
is
complete or
i
n progre
ss.
The
s
e three
bi
t
s
a
re d
is
c
uss
ed f
i
r
s
t
.
DQ7: Data# Poll
i
n
g
The Am2
9
BDD160 fe
a
t
u
re
s
a
D
a
t
a
# poll
i
ng fl
a
g
as
a
method to
i
nd
i
c
a
te to the ho
s
t
s
y
s
tem whether the em-
b
edded
a
lgor
i
thm
s
a
re
i
n progre
ss
or
a
re complete
.
D
u
r
i
ng the Em
b
edded Progr
a
m Algor
i
thm
a
n
a
ttempt
to re
a
d the
ba
nk
i
n wh
i
ch progr
a
mm
i
ng w
as
i
n
i
t
ia
ted
w
i
ll prod
u
ce the complement of the d
a
t
a
l
as
t wr
i
tten to
DQ7
.
Upon complet
i
on of the Em
b
edded Progr
a
m Al-
gor
i
thm,
a
n
a
ttempt to re
a
d the dev
i
ce w
i
ll prod
u
ce the
tr
u
e l
as
t d
a
t
a
wr
i
tten to DQ7
.
Note th
a
t DATA# poll
i
ng
ret
u
rn
s
i
nv
a
l
i
d d
a
t
a
for the
a
ddre
ss
b
e
i
ng progr
a
mmed
or er
as
ed
.
For ex
a
mple, the d
a
t
a
re
a
d for
a
n
a
ddre
ss
pro-
gr
a
mmed
as
0000 0000 1000 0000
b
w
i
ll ret
u
rn XXXX
XXXX 0XXX XXXX
b
d
u
r
i
ng
a
n Em
b
edded Progr
a
m
oper
a
t
i
on
.
Once the Em
b
edded Progr
a
m Algor
i
thm
is
complete, the tr
u
e d
a
t
a
is
re
a
d
ba
ck on DQ7
.
Note th
a
t
a
t the
i
n
s
t
a
nt when DQ7
s
w
i
tche
s
to tr
u
e d
a
t
a
, the
other
bi
t
s
m
a
y not yet
b
e tr
u
e
.
However, they w
i
ll
a
ll
b
e
tr
u
e d
a
t
a
on the next re
a
d from the dev
i
ce
.
Ple
as
e
note th
a
t D
a
t
a
# poll
i
ng m
a
y g
i
ve m
is
le
a
d
i
ng
s
t
a
t
us
when
a
n
a
ttempt
is
m
a
de to wr
i
te to
a
protected
s
ec-
tor
.
For ch
i
p er
as
e, the D
a
t
a
# poll
i
ng fl
a
g
is
v
a
l
i
d
a
fter the
r
isi
ng edge of the
si
xth WE# p
u
l
s
e
i
n the
si
x wr
i
te
p
u
l
s
e
s
e
qu
ence
.
For
s
ector er
as
e, the D
a
t
a
# poll
i
ng
is
v
a
l
i
d
a
fter the l
as
t r
isi
ng edge of the
s
ector er
as
e WE#
p
u
l
s
e
.
D
a
t
a
# poll
i
ng m
us
t
b
e performed
a
t
s
ector
a
d-
dre
ss
e
s
w
i
th
i
n
a
ny of the
s
ector
s
b
e
i
ng er
as
ed
a
nd not
a
s
ector th
a
t
is
a
protected
s
ector
.
Otherw
is
e, the
s
t
a
-
t
us
m
a
y not
b
e v
a
l
i
d
.
DQ7 = 0 d
u
r
i
ng
a
n Em
b
edded
Er
as
e Algor
i
thm (ch
i
p er
as
e or
s
ector er
as
e oper
a
t
i
on)
bu
t w
i
ll ret
u
rn
a
“1”
a
fter the oper
a
t
i
on complete
s
b
e-
c
aus
e
i
t w
i
ll h
a
ve dropped
ba
ck
i
nto re
a
d mode
.
In
as
ynchrono
us
mode,
jus
t pr
i
or to the complet
i
on of
the Em
b
edded Algor
i
thm oper
a
t
i
on
s
, DQ7 m
a
y
ch
a
nge
as
ynchrono
us
ly wh
i
le OE#
is
ass
erted low
.
(In
s
ynchrono
us
mode, ADV# exh
ibi
t
s
th
is
b
eh
a
v
i
or
.
) The
s
t
a
t
us
i
nform
a
t
i
on m
a
y
b
e
i
nv
a
l
i
d d
u
r
i
ng the
i
n
s
t
a
nce
of tr
a
n
si
t
i
on from
s
t
a
t
us
i
nform
a
t
i
on to
a
rr
a
y (memory)
d
a
t
a.
An extr
a
v
a
l
i
d
i
ty check
is
therefore
s
pec
i
f
i
ed
i
n
the d
a
t
a
poll
i
ng
a
lgor
i
thm
.
The v
a
l
i
d
a
rr
a
y d
a
t
a
on
DQ
3
1–DQ0 (DQ15–DQ0 when WORD# = 0)
is
a
v
ai
l-
ab
le for re
a
d
i
ng on the next
su
cce
ssi
ve re
a
d
a
ttempt
.
The D
a
t
a
# poll
i
ng fe
a
t
u
re
is
only
a
ct
i
ve d
u
r
i
ng the Em-
b
edded Progr
a
mm
i
ng Algor
i
thm, Em
b
edded Er
as
e Al-
gor
i
thm, Er
as
e
Sus
pend, Er
as
e
Sus
pend-Progr
a
m
mode, or
s
ector er
as
e t
i
me-o
u
t
.
If the
us
er
a
ttempt
s
to wr
i
te to
a
protected
s
ector,
D
a
t
a
# poll
i
ng w
i
ll
b
e
a
ct
i
v
a
ted for
ab
o
u
t 1
μs:
the de-
v
i
ce w
i
ll then ret
u
rn to re
a
d mode, w
i
th the d
a
t
a
from
the protected
s
ector
u
nch
a
nged
.
If the
us
er
a
ttempt
s
to er
as
e
a
protected
s
ector, Toggle B
i
t (DQ6) w
i
ll
b
e
a
ct
i
v
a
ted for
ab
o
u
t 150
μs;
the dev
i
ce w
i
ll then ret
u
rn
to re
a
d mode, w
i
tho
u
t h
a
v
i
ng er
as
ed the protected
s
ector
.
T
ab
le 2
3
s
how
s
the o
u
tp
u
t
s
for D
a
t
a
# Poll
i
ng on DQ7
.
F
i
g
u
re 6
s
how
s
the D
a
t
a
# Poll
i
ng
a
lgor
i
thm
.
F
i
g
u
re 27
s
how
s
the t
i
m
i
ng d
ia
gr
a
m for
s
ynchrono
us
s
t
a
t
us
DQ7
d
a
t
a
poll
i
ng
.
RY/BY#: Ready/Bu
s
y#
The dev
i
ce prov
i
de
s
a
RY/BY# open dr
ai
n o
u
tp
u
t p
i
n
as
a
w
a
y to
i
nd
i
c
a
te to the ho
s
t
s
y
s
tem th
a
t the Em
b
edded
Algor
i
thm
s
a
re e
i
ther
i
n progre
ss
or h
a
ve
b
een com-
pleted
.
If the o
u
tp
u
t
is
low, the dev
i
ce
is
bus
y w
i
th e
i
ther
a
progr
a
m, er
as
e, or re
s
et oper
a
t
i
on
.
If the o
u
tp
u
t
is
flo
a
t
i
ng, the dev
i
ce
is
re
a
dy to
a
ccept
a
ny re
a
d/wr
i
te or
er
as
e oper
a
t
i
on
.
When the RY/BY# p
i
n
is
low, the de-
v
i
ce w
i
ll not
a
ccept
a
ny
a
dd
i
t
i
on
a
l progr
a
m or er
as
e
comm
a
nd
s
w
i
th the except
i
on of the Er
as
e
sus
pend
comm
a
nd
.
If the dev
i
ce h
as
entered Er
as
e
Sus
pend
mode, the RY/BY# o
u
tp
u
t w
i
ll
b
e flo
a
t
i
ng
.
For progr
a
m-
m
i
ng, the RY/BY#
is
v
a
l
i
d (RY/BY# = 0)
a
fter the r
isi
ng
edge of the fo
u
rth WE# p
u
l
s
e
i
n the fo
u
r wr
i
te p
u
l
s
e
s
e-
qu
ence
.
For ch
i
p er
as
e, the RY/BY#
is
v
a
l
i
d
a
fter the
r
isi
ng edge of the
si
xth WE# p
u
l
s
e
i
n the
si
x wr
i
te p
u
l
s
e
s
e
qu
ence
.
For
s
ector er
as
e, the RY/BY#
is
a
l
s
o v
a
l
i
d
a
fter the r
isi
ng edge of the
si
xth WE# p
u
l
s
e
.
If RE
S
ET#
is
ass
erted d
u
r
i
ng
a
progr
a
m or er
as
e oper-
a
t
i
on, the RY/BY# p
i
n rem
ai
n
s
a
“0” (
bus
y)
u
nt
i
l the
i
n-
tern
a
l re
s
et oper
a
t
i
on
is
complete, wh
i
ch re
qui
re
s
a
t
i
me of t
READY
(d
u
r
i
ng Em
b
edded Algor
i
thm
s
)
.
The
s
y
s
-
tem c
a
n th
us
mon
i
tor RY/BY# to determ
i
ne whether the
re
s
et oper
a
t
i
on
is
complete
.
If RE
S
ET#
is
ass
erted
when
a
progr
a
m or er
as
e oper
a
t
i
on
is
not exec
u
t
i
ng
(RY/BY# p
i
n
is
“flo
a
t
i
ng”), the re
s
et oper
a
t
i
on
is
com-
pleted
i
n
a
t
i
me of t
READY
(not d
u
r
i
ng Em
b
edded Algo-
r
i
thm
s
)
.
The
s
y
s
tem c
a
n re
a
d d
a
t
a
t
RH
a
fter the
RE
S
ET# p
i
n ret
u
rn
s
to V
IH
.
Si
nce the RY/BY# p
i
n
is
a
n open-dr
ai
n o
u
tp
u
t,
s
ever
a
l
RY/BY# p
i
n
s
c
a
n
b
e t
i
ed together
i
n p
a
r
a
llel w
i
th
a
p
u
ll-
u
p re
sis
tor to V
CC
.
An extern
a
l p
u
ll-
u
p re
sis
tor
is
re-
qui
red to t
a
ke RY/BY# to
a
V
IH
level
si
nce the o
u
tp
u
t
is
a
n open dr
ai
n
.
T
ab
le 2
3
s
how
s
the o
u
tp
u
t
s
for RY/BY#
.
F
i
g
u
re
s
15, 1
9
,
21
a
nd 22
s
how
s
RY/BY# for re
a
d, re
s
et, progr
a
m,
a
nd
er
as
e oper
a
t
i
on
s
, re
s
pect
i
vely
.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| AM29BDD160GB17CPBE | 16 Megabit (1 M x 16-bit/512 K x 32-Bit), CMOS 2.5 Volt-only Burst Mode, Dual Boot, Simultaneous Read/Write Flash Memory |
| AM29BDD160GB17CPBF | 16 Megabit (1 M x 16-bit/512 K x 32-Bit), CMOS 2.5 Volt-only Burst Mode, Dual Boot, Simultaneous Read/Write Flash Memory |
| AM29BDD160GB17CPBI | 16 Megabit (1 M x 16-bit/512 K x 32-Bit), CMOS 2.5 Volt-only Burst Mode, Dual Boot, Simultaneous Read/Write Flash Memory |
| AM29BDD160GB17CPBK | 16 Megabit (1 M x 16-bit/512 K x 32-Bit), CMOS 2.5 Volt-only Burst Mode, Dual Boot, Simultaneous Read/Write Flash Memory |
| AM29BDD160GB17DKF | 16 Megabit (1 M x 16-bit/512 K x 32-Bit), CMOS 2.5 Volt-only Burst Mode, Dual Boot, Simultaneous Read/Write Flash Memory |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| AM29BDS128HE9VKI | 制造商:Advanced Micro Devices 功能描述:Flash Mem Parallel/Serial 1.8V 128M-Bit 8M x 16 50ns 80-Pin FBGA |
| AM29BDS643GT5KVAI | 制造商:Spansion 功能描述:FLASH PARALLEL 1.8V 64MBIT 4MX16 55NS 44FBGA - Trays |
| AM29BL802CB-65RZET | 制造商:Spansion 功能描述: |
| AM29C01WW WAF | 制造商:Advanced Micro Devices 功能描述: |
| AM29C10API | 制造商:Rochester Electronics LLC 功能描述:- Bulk |
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