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| 型號： | AM29BDD160GB17CKK |
| 廠商： | Advanced Micro Devices, Inc. |
| 英文描述： | 16 Megabit (1 M x 16-bit/512 K x 32-Bit), CMOS 2.5 Volt-only Burst Mode, Dual Boot, Simultaneous Read/Write Flash Memory |
| 中文描述： | 16兆位（1 M中的x 16-bit/512畝× 32位），2.5伏的CMOS只突發(fā)模式，雙啟動，同步讀/寫閃存 |
| 文件頁數(shù)： | 47/79頁 |
| 文件大?。?/td> | 1368K |
| 代理商： | AM29BDD160GB17CKK |
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June 7, 2006
Am29BDD160G
45
Legend:
BA = Addre
ss
of the
ba
nk th
a
t
is
b
e
i
ng
s
w
i
tched to
au
to
s
elect mode,
is
i
n
b
yp
ass
mode, or
is
b
e
i
ng er
as
ed
.
Determ
i
ned
b
y A18
a
nd A17,
s
ee T
ab
le
s
11
a
nd 12 for more det
ai
l
.
PA = Progr
a
m Addre
ss
(A18
:
A0)
.
Addre
ss
e
s
l
a
tch on the f
a
ll
i
ng edge
of the WE# or CE# p
u
l
s
e, wh
i
chever h
a
ppen
s
l
a
ter
.
PD = Progr
a
m D
a
t
a
(DQ31
:
DQ0) wr
i
tten to loc
a
t
i
on PA
.
D
a
t
a
l
a
tche
s
on the r
isi
ng edge of WE# or CE# p
u
l
s
e, wh
i
chever h
a
ppen
s
f
i
r
s
t
.
RA = Re
a
d Addre
ss
(A18
:
A0)
.
RD = Re
a
d D
a
t
a
(DQ31
:
DQ0) from loc
a
t
i
on RA
.
SA = Sector Addre
ss
(A18
:
A11) for ver
i
fy
i
ng (
i
n
au
to
s
elect mode),
er
asi
ng, or
a
pply
i
ng
s
ec
u
r
i
ty comm
a
nd
s.
WD = Wr
i
te D
a
t
a.
See “Conf
i
g
u
r
a
t
i
on Reg
is
ter” def
i
n
i
t
i
on for
s
pec
i
f
i
c
wr
i
te d
a
t
a.
D
a
t
a
l
a
tched on r
isi
ng edge of WE#
.
X = Don’t c
a
re
Notes:
1
.
2
.
3
.
See T
ab
le 1 for de
s
cr
i
pt
i
on of
bus
oper
a
t
i
on
s.
All v
a
l
u
e
s
a
re
i
n hex
a
dec
i
m
a
l
.
Sh
a
ded cell
s
i
n t
ab
le denote re
a
d cycle
s.
All other cycle
s
a
re
wr
i
te oper
a
t
i
on
s.
D
u
r
i
ng
u
nlock cycle
s
, (lower
a
ddre
ss
bi
t
s
a
re 555 or 2AAh
as
s
hown
i
n t
ab
le)
a
ddre
ss
bi
t
s
h
i
gher th
a
n A11 (except where BA
is
re
qui
red)
a
nd d
a
t
a
bi
t
s
h
i
gher th
a
n DQ7
a
re don’t c
a
re
s.
No
u
nlock or comm
a
nd cycle
s
re
qui
red when
ba
nk
is
re
a
d
i
ng
a
rr
a
y d
a
t
a.
The Re
s
et comm
a
nd
is
re
qui
red to ret
u
rn to the re
a
d mode (or to
the er
as
e-
sus
pend-re
a
d mode
i
f prev
i
o
us
ly
i
n Er
as
e S
us
pend)
when
a
ba
nk
is
i
n the
au
to
s
elect mode, or
i
f DQ5 goe
s
h
i
gh (wh
i
le
the
ba
nk
is
prov
i
d
i
ng
s
t
a
t
us
i
nform
a
t
i
on)
.
The fo
u
rth cycle of the
au
to
s
elect comm
a
nd
s
e
qu
ence
is
a
re
a
d
cycle
.
The
s
y
s
tem m
us
t prov
i
de the
ba
nk
a
ddre
ss
to o
b
t
ai
n the
m
a
n
u
f
a
ct
u
rer ID or dev
i
ce ID
i
nform
a
t
i
on
.
See the
A
u
to
s
elect
Comm
a
nd
s
ect
i
on for more
i
nform
a
t
i
on
.
Th
is
comm
a
nd c
a
nnot
b
e exec
u
ted
u
nt
i
l The Unlock Byp
ass
comm
a
nd m
us
t
b
e exec
u
ted
b
efore wr
i
t
i
ng th
is
comm
a
nd
s
e
qu
ence
.
The Unlock Byp
ass
Re
s
et comm
a
nd m
us
t
b
e
exec
u
ted to ret
u
rn to norm
a
l oper
a
t
i
on
.
4
.
5
.
6
.
7
.
8
.
9
.
Th
is
comm
a
nd
is
i
gnored d
u
r
i
ng
a
ny em
b
edded progr
a
m, er
as
e
or
sus
pended oper
a
t
i
on
.
10
.
V
a
l
i
d re
a
d oper
a
t
i
on
s
i
ncl
u
de
as
ynchrono
us
a
nd
bu
r
s
t re
a
d mode
oper
a
t
i
on
s.
11
.
The dev
i
ce ID m
us
t
b
e re
a
d
a
cro
ss
the fo
u
rth, f
i
fth,
a
nd
si
xth
cycle
s.
00h
i
n the
si
xth cycle
i
nd
i
c
a
te
s
top
b
oot
b
lock, 01h
i
nd
i
c
a
te
s
b
ottom
b
oot
b
lock
.
12
.
The
s
y
s
tem m
a
y re
a
d
a
nd progr
a
m
i
n non-er
asi
ng
s
ector
s
, or
enter the
au
to
s
elect mode, when
i
n the Progr
a
m/Er
as
e S
us
pend
mode
.
The Progr
a
m/Er
as
e S
us
pend comm
a
nd
is
v
a
l
i
d only
d
u
r
i
ng
a
s
ector er
as
e oper
a
t
i
on,
a
nd re
qui
re
s
the
ba
nk
a
ddre
ss.
13
.
The Progr
a
m/Er
as
e Re
su
me comm
a
nd
is
v
a
l
i
d only d
u
r
i
ng the
Er
as
e S
us
pend mode,
a
nd re
qui
re
s
the
ba
nk
a
ddre
ss.
14
.
Comm
a
nd
is
v
a
l
i
d when dev
i
ce
is
re
a
dy to re
a
d
a
rr
a
y d
a
t
a
or
when dev
i
ce
is
i
n
au
to
s
elect mode
.
15
.
A
s
ynchrono
us
re
a
d oper
a
t
i
on
s.
16
.
ACC m
us
t
b
e
a
t V
ID
d
u
r
i
ng the ent
i
re oper
a
t
i
on of th
is
comm
a
nd
.
17
.
Comm
a
nd
is
i
gnored d
u
r
i
ng
a
ny Em
b
edded Progr
a
m, Em
b
edded
Er
as
e, or S
us
pend oper
a
t
i
on
.
18
.
The Unlock Byp
ass
Entry comm
a
nd
is
re
qui
red pr
i
or to
a
ny
Unlock Byp
ass
oper
a
t
i
on
.
The Unlock Byp
ass
Re
s
et comm
a
nd
is
re
qui
red to ret
u
rn to the re
a
d mode
.
Table 19
.
Memory Array Command Def
i
n
i
t
i
on
s
(x
3
2 Mode)
Command (Note
s
)
s
Bu
s
Cycle
s
(Note
s
1–4)
Th
i
rd
Addr
Data
F
i
r
s
t
S
econd
Fourth
Addr
F
i
fth
Si
xth
Addr Data Addr Data
RA
RD
XXX
F0
555
AA
555
AA
555
AA
555
AA
555
AA
BA
B0
BA
3
0
55
98
XX
A0
555
AA
555
AA
555
AA
XX
A0
XX
8
0
XX
98
XX
9
0
Data
Addr
Data
Addr
Data
Re
a
d (5)
Re
s
et (6)
A
u
to
s
elect
(7)
Progr
a
m
Ch
i
p Er
as
e
S
ector Er
as
e
Progr
a
m/Er
as
e
Sus
pend (12)
Progr
a
m/Er
as
e Re
su
me (1
3
)
CFI Q
u
ery (14, 15)
Acceler
a
ted Progr
a
m (16)
Conf
i
g
u
r
a
t
i
on Reg
is
ter Ver
i
fy (15)
Conf
i
g
u
r
a
t
i
on Reg
is
ter Wr
i
te (17)
Unlock Byp
ass
Entry (1
8
)
Unlock Byp
ass
Progr
a
m (1
8
)
Unlock Byp
ass
Er
as
e (1
8
)
Unlock Byp
ass
CFI (14, 1
8
)
Unlock Byp
ass
Re
s
et (1
8
)
1
1
4
6
4
6
6
1
1
1
2
3
4
3
2
2
1
2
M
a
n
u
f
a
ct
u
rer ID
Dev
i
ce ID (11)
2AA
2AA
2AA
2AA
2AA
55
55
55
55
55
555
555
555
555
555
9
0
9
0
A0
8
0
8
0
(BA)X00
(BA)X01
PA
555
555
01
7E
PD
AA
AA
(BA)X0E
0
8
(BA)X0F 00/01
2AA
2AA
55
55
555
S
A
10
3
0
PA
2AA
2AA
2AA
PA
XX
PD
55
55
55
PD
10
(BA)555
555
555
C6
D0
20
(BA)XX
XX
RD
WD
XX
00
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