參數(shù)資料
型號(hào)： AM29BDD160G
廠商： Advanced Micro Devices, Inc.
英文描述： 16 Megabit (1 M x 16-bit/512 K x 32-Bit), CMOS 2.5 Volt-only Burst Mode, Dual Boot, Simultaneous Read/Write Flash Memory
中文描述： 16兆位（1 M中的x 16-bit/512畝× 32位），2.5伏的CMOS只突發(fā)模式，雙啟動(dòng)，同步讀/寫閃存
文件頁數(shù)： 5/80頁
文件大小： 3476K
代理商： AM29BDD160G
Am29BDD160G
3
TABLE OF CONTENTS
Product Selector Guide. . . . . . . . . . . . . . . . . . . . . . 3
BLOCK DIAGRAM . . . . . . . . . . . . . . . . . . . . . . . . . 3
BLOCK DIAGRAM OF SIMULTANEOUS
OPERATION CIRCUIT . . . . . . . . . . . . . . . . . . . . . 4
Connection Diagram. . . . . . . . . . . . . . . . . . . . . . . . 5
80-Ball Fortified BGA . . . . . . . . . . . . . . . . . . . . . . . 6
Special Package Handling Instructions ............................................6
Pin Configuration. . . . . . . . . . . . . . . . . . . . . . . . . . . 7
LOGIC SYMBOLS ......................................................................7
X16 Mode ...................................................................................................7
X32 Mode ...................................................................................................7
Ordering Information ................................................................8
Device Bus Operations . . . . . . . . . . . . . . . . . . . . . . 9
Table 1. Device Bus Operation ......................................................10
Versatile I/O (VIO) Control .................................................11
Word/Double Word Configuration ................................................11
Requirements for Reading Array Data ...........................................11
Simultaneous Read/Write Operations Overview
and Restrictions .........................................................................11
Restrictions .............................................................................................11
Table 2. Table 2. Bank Assignment for Boot Bank
Sector Devices
.................................11
Simultaneous Read/Write Operations With
Zero Latency ...............................................................................11
Table 3. Top Boot Bank Select
.....................12
Table 4. Bottom Boot Bank Select
..................12
Writing Commands/Command Sequences ......................12
Accelerated Program and Erase Operations ................................12
Autoselect Functions ...........................................................................12
Automatic Sleep Mode (ASM) ..............................................12
Standby Mode ............................................................................12
RESET#: Hardware Reset Pin ...............................................13
Output Disable Mode ..............................................................13
Autoselect Mode ......................................................................13
Table 5. Am29BDD160 Autoselect Codes (High
Voltage Method) .................................................................................14
Asynchronous Read Operation (Non-Burst) ................. 14
Figure 1. Asynchronous Read Operation ................................... 14
Synchronous (Burst) Read Operation .................................15
Linear Burst Read Operations ..............................................15
Table 6. 16-Bit and 32-Bit Linear and Burst Data Order .......15
CE# Control in Linear Mode ............................................................16
ADV# Control In Linear Mode ........................................................16
RESET# Control in Linear Mode .....................................................16
OE# Control in Linear Mode ...........................................................16
IND/WAIT# Operation in Linear Mode .......................................16
Table 7. Valid Configuration Register Bit Definition for IND/
WAIT# ..................................................................................................17
Figure 2. End of Burst Indicator (IND/WAIT#) Timing
for Linear 8-Word Burst Operation .......................................... 17
Burst Access Timing Control ................................................18
Initial Burst Access Delay Control .................................................18
Table 8. Burst Initial Access Delay ...............................................18
Figure 3. Initial Burst Delay Control ........................................... 18
Burst CLK Edge Data Delivery ............................................. 19
Burst Data Hold Control ...................................................................19
Asserting RESET# During A Burst Access ...................................19
Configuration Register ........................................................... 19
Table 9. Configuration Register Definitions ..............................19
Table 10. Configuration Register After Device Reset ............20
Initial Access Delay Configuration .................................................20
SECTOR PROTECTION .....................................................20
Sector and Sector Groups ................................................................20
Persistent Sector Protection ...........................................................20
Password Sector Protection ............................................................20
WP# Hardware Protection ..............................................................20
Persistent Sector Protection ................................................ 21
Persistent Protection Bit (PPB) ........................................................21
Persistent Protection Bit Lock (PPB Lock) ...................................21
Dynamic Protection Bit (DYB) ........................................................21
Table 11. Sector Protection Schemes ..........................................22
Persistent Sector Protection Mode Locking Bit ............22
Password Protection Mode .................................................22
Password and Password Mode Locking Bit ....................22
64-bit Password ................................................................................... 23
Write Protect (WP#) .............................................................23
SecSi (Secured Silicon) Sector Protection .....................23
SecSi Sector Protection Bit ...................................................23
Persistent Protection Bit Lock ............................................24
Hardware Data Protection ..................................................24
Low VCC Write Inhibit .....................................................................24
Write Pulse “Glitch” Protection ....................................................24
Logical Inhibit ........................................................................................24
Power-Up Write Inhibit ....................................................................24
VCC and VIO Power-up And Power-down Sequencing .........24
Table 12. Sector Addressees for Top Boot Sector
Devices .................................................................................................24
Table 13. Sector Addresses for Bottom Boot Sector
Devices .................................................................................................26
Common Flash Memory Interface (CFI). . . . . . . 28
Table 14. CFI Query Identification String ...................................28
Table 15. CFI System Interface String ..........................................28
Table 16. CFI Device Geometry Definition ...............................29
Table 17. CFI Primary Vendor-Specific Extended
Query ...................................................................................................29
Command Definitions ...............................................................31
Reading Array Data in Non-burst Mode ...........................31
Reading Array Data in Burst Mode .....................................31
Read/Reset Command ...........................................................32
Autoselect Command ............................................................32
Program Command Sequence .............................................32
Accelerated Program Command ........................................32
Unlock Bypass Command Sequence ..................................33
Figure 4. Program Operation ....................................................... 33
Unlock Bypass Entry Command ..........................................33
Unlock Bypass Program Command ...................................33
Unlock Bypass Chip Erase Command ...........................................34
Unlock Bypass CFI Command .........................................................34
Chip Erase Command ............................................................34
Sector Erase Command .........................................................34
Figure 5. Erase Operation ............................................................. 35
Sector Erase and Program Suspend Command .............35
Sector Erase and Program Suspend Operation
Mechanics ...................................................................................35
Table 18. Allowed Operations During Erase/Program
Suspend .................................................................................................35
Sector Erase and Program Resume Command ..............36
Configuration Register Read Command ..........................36
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