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參數(shù)資料
| 型號(hào)： | Alpha 21164 |
| 廠商： | SAMSUNG SEMICONDUCTOR CO. LTD. |
| 英文描述： | Alpha Microprocessor(64位微處理器) |
| 中文描述： | 阿爾法微處理器（64位微處理器） |
| 文件頁(yè)數(shù)： | 40/115頁(yè) |
| 文件大?。?/td> | 846K |
| 代理商： | ALPHA 21164 |
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21164 Microprocessor Functional Overview
Board-Level Backup Cache Interface
The Bcache system supports block sizes of 32 bytes or 64 bytes but it be must set
like the secondary cache (Scache). The block size is selected by a mode bit. The
Scache is 3-way, set-associative but is a subset of the larger externally implemented,
direct-mapped Bcache. In systems with no Bcache, the Scache block size must be set
to 64 bytes.
5.2.1 Bcache Victim Buffers
The 21164 is designed to support systems with one or more offchip Bcache victim
buffers. External victim buffers improve the overall performance of the Bcache. A
Bcache victim is generated when the 21164 deallocates a dirty block from the
Bcache. Each time a Bcache victim is produced, the 21164 stops reading the Bcache
until the system takes the current victim, and then the Bcache operations resume.
5.2.2 Cache Coherence Protocol
Cache coherency is a concern for single and multiprocessor 21164-based systems as
there may be several caches on a processor module and several more in multiproces-
sor systems.
The system hardware designer need not be concerned about Icache and Dcache
coherency. Coherency of the Icache is a software concern—it is flushed with an IMB
(PALcode) instruction. The 21164 maintains coherency between the Dcache and the
Scache.
If the system does not have a Bcache, the system designer must create mechanisms
in the system interface logic to support cache coherency between the Scache, main
memory, and other caches in the system.
If the system has a Bcache, the 21164 maintains cache coherency between the
Scache and the Bcache. The Scache is a subset of the Bcache. In this case, the
designer must create mechanisms in the system interface logic to support cache
coherency between the Bcache, main memory, and other caches in the system.
The following tasks must be performed to maintain cache coherency:
The CBU in the 21164 maintains coherency in the Dcache and keeps it as a sub-
set of the Scache.
If an optional Bcache is present, then the 21164 maintains the Scache as a subset
of the Bcache. The Scache is set-associative but is kept a subset of the larger
externally implemented direct-mapped Bcache.
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