參數(shù)資料
型號： AL1402
廠商： Electronic Theatre Controls, Inc.
元件分類： 圓形連接器
英文描述： Circular Connector; No. of Contacts:100; Series:MS27497; Body Material:Aluminum; Connecting Termination:Crimp; Connector Shell Size:22; Circular Contact Gender:Pin; Circular Shell Style:Wall Mount Receptacle RoHS Compliant: No
中文描述： OPTOREC轉(zhuǎn)爐
文件頁數(shù)： 3/8頁
文件大?。?/td> 156K
代理商： AL1402
Alesis Semiconductor
12555 J efferson Blvd., Suite 285
Los Angeles, CA 90066
Fax (310) 306-1551
- 3 -
DS1402-0702
Phone (310) 301-0780
www.alesis-semi.com
Master and Slave Modes
Master Mode:
All
outputs
optical format data stream on the OPDIGIN
(pin 6). WDCLK is an output.
are derived
from
the input
Slave Mode:
DAC outputs, USER
SVCO outputs are synchronized to WDCLK,
which is an input.
outputs, BCLK
and
In
arbitrary phase with respect to the incoming
samples of OPDIGIN, but if the frequencies
aren’t identical samples will be dropped,
repeated, or garbled.
frequencies are achieved by either: using
DVCO (pin 18) as the source from which
WDCLK is generated, or creating OPDIGIN
from a source synchronized to WDCLK.
Slave mode,
WDCLK
may
be at
an
Generally, identical
Use
The AL1402 OptoRec interface has been
designed for ease of use and flexibility in
systems designed to interface to the ADAT
protocol. It supports both left and right
justified data formats for ease of integration
into existing devices as well as new devices.
These formats allow it to operate in parallel
with many standard ADC’s.
The designer uses the FMT0, FMT1, MODE0
and
MODE1
pins
to select
format and mode.
the
desired
The format pins are summarized in Table 3,
Formats. The AL1402 provides support for
both the ADAT
Type I format (16-bit) and
the ADAT
Type II format (20-bit).
output is 24 bit.
Data input lengths up to
24 bits is supported.
Data
USER0 is used to receive the ADAT
32-bit timcode; USER1 is used to receive
MIDI data (if the source device supports
these features). USER2
reserved and should not be used.
format
and
USER3
are
Table 3 Formats
FMT1
0
0
1
1
FMT0
0
1
0
1
Format
OUT data is right justified, BCLK falls on changing WDCLK
OUT data is left justified, BCLK rises on changing WDCLK
Chip Reset
Gated BLCK, BCLK rises on changing WDCLK
Table 4 Modes
MODE1
0
MODE0
0
Mode
Master mode, WDCLK is an output
Slave mode, WDCLK is an input. WDCLK MUST be derived from the same clock
supplying the source
Reserved
Reserved
0
1
1
1
0
1
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